Intel Corporation

Vipul V Mehta

Ziyin Lin

Rahul Jain

Edvin Cetegen

Rahul N Manepalli

Kyu Oh Lee

Amruthavalli Pallavi Alur

Sai Vadlamani

Wei-Lun Kane Jen

Siddharth K Alur

Sri Chaitra J Chavali

Ashish Dhall

Eric Jin Li

Nisha Ananthakrishnan

Yiqun Bai

Shan Zhong

Robert L Sankman

Debendra Mallik

Sanka Ganesan

Digvijay Ashokkumar Raorane

Tarek A Ibrahim

Sergio Antonio Chan Arguedas

Nicholas S Haehn

Steve S Cho

Nicholas Neal

Thomas Heaton

John Decker

Yuying Wei

Jacob Vehonsky

Antariksh Rao Pratap Singh

Sushrutha Reddy Gujjula

Wei Ey Li

Christopher L Rumer

Xavier Francois Brun

Sandeep Razdan

Yan Li

Bassam Mohammed Ziadeh

Rajen S Sidhu

John J Beatty

Suriyakala Ramalingam

Taylor W Gaines

Elizabeth Nofen

Suzana Prstic

Wei Tan

Sivakumar Nagarajan

Hsin-Wei Wang

Yang Guo

Jingyi Huang

Joseph Van Nausdle

Soud Choudhury

Ifeanyi Okafor

Nai-Yuan Liu

Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

Protruding SN substrate features for epoxy flow control

An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

Package with underfill containment barrier

Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

Hydrophobic feature to control adhesive flow

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

Barrier structures for underfill containment

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.

Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap

An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.

High thermal conductivity, high modulus structure within a mold material layer of an integrated circuit package

Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.

Trenches in wafer level packages for improvements in warpage reliability and thermals

A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material.

Semiconductor die package with warpage management and process for forming such

Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

Semiconductor package having wafer-level active die and external die mount

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.

Growing community of inventors

Chandler, AZ, United States of America

Vipul V Mehta