Micron Technology Incorporated

Vipul Patel

Theodore T Pekny

Stephen J Gualandri

Ezra E Hartz

Scott Anthony Stoller

Pitamber Shukla

Priya Venkataraman

Stephen Gualandri

A memory device including control logic to identify a command issued to the memory device to execute a memory access operation on one or more memory cells of a memory array of the memory device. The control logic determines a command type associated with the command and identifies, based on the command type, a subset of target information to be stored as part of a set of command information. The control logic stores, in a data store of the memory device, the set of command information associated with the command.

Memory device command history management

Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.

Systems and methods involving hardware-based reset of unresponsive memory devices

Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.

Read calibration by sector of memory

Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

Reduced-voltage operation of a memory device

The present disclosure includes apparatuses and methods for providing indications associated with power management events. An example apparatus may include a plurality of memory units coupled to a shared power management signal. In this example apparatus, each of the plurality of memory units may be configured to provide to the other of the plurality of memory units, via the shared power management signal, an indication of whether the one of the plurality of memory units is entering a power management event. Further, each of the plurality of memory units may be configured to, if the one of the plurality of memory units is entering the power management event, an indication of a particular operation type associated with the power management event.

Apparatuses and methods for indicating an entrance of a power management event

A memory includes a memory array comprising a plurality of pages and a page buffer. The page buffer includes first registers, second registers, compare logic, and third registers. The first registers store data read from a page of the memory array. The second registers store a user pattern. The compare logic compares the data stored in the first registers to the user pattern stored in the second registers. The third registers store the comparison results.

Memory including search logic

Memories including a controller configured to cause the memory to read a plurality of memory cells using a read voltage having a particular voltage level, determine a number of memory cells of a first subset of memory cells of the plurality of memory cells having a particular data state in response to the read voltage having the particular voltage level, and in response to determining that the number of memory cells of the first subset of memory cells having the particular data state is less than a particular threshold, adjust the voltage level of the read voltage based on the number of memory cells of the first subset of memory cells having the particular data state, and re-read the plurality of memory cells using the read voltage having the adjusted voltage level.

Charge loss failure mitigation

Apparatuses and methods for indicating an operation type associated with a power management event

Memories, and systems incorporating similar memories, as well as their operation, where the memory might include an array of memory cells, a status register, and a controller configured to access the array of memory cells. The controller may further be configured to perform a plurality of read operations on the array of memory cells in response to a read command associated with a plurality of addresses, store a particular value to the status register in response to data of a particular read operation corresponding to a particular address of the plurality of addresses being available for readout by an external device, and store a different value to the status register in response to data of a different read operation corresponding to a different address of the plurality of addresses being available for readout by the external device.

Memories for reading data corresponding to multiple addresses associated with a read command

A memory includes a memory array comprising a plurality of pages, a page buffer, and search logic. The page buffer includes first registers, second registers, compare logic, and third registers. The first registers store data read from a page of the memory array. The second registers store a user pattern. The compare logic compares the data stored in the first registers to the user pattern stored in the second registers. The third registers store the comparison results. The search logic is configured to identify addresses of the memory array where the comparison results stored in the third registers indicate a match between the data read from the page and column of the memory array and the user pattern. The first registers are loaded with data from a following page of the memory array concurrently with the search logic identifying addresses indicating a match in a previous page of the memory array.

Methods of operating a memory include reading a particular grouping of memory cells using a read voltage having a particular voltage level, determining a number of memory cells of a subset of memory cells of the particular grouping of memory cells having a particular data state, and, if the number of memory cells of the subset of memory cells having the particular data state is less than a particular threshold, adjusting a voltage level of the read voltage in response to the number of memory cells of the subset of memory cells having the particular data state and reading the particular grouping of memory cells using the read voltage having the adjusted voltage level.

Growing community of inventors

Santa Clara, CA, United States of America

Vipul Patel