United States of America As Represented by the Secretary of the Air Force

Vipul J Patel

Waleed Khalil

Brian Dupaix

Jamin McCue

Tony K Quach

John M Emmert

James H Wilson

Steven R Dooley

Sidharth Balasubramanian

In accordance with various embodiments of the disclosed subject matter, a system, apparatus and method is configured to provide a poly-phased, time-interleaved radio frequency (RF) digital-to-analog converter (DAC) suitable for use in radar, radio, mobile and other RF systems.

Poly phased, time-interleaved RF-DAC for multi-function frequency-agile, tunable transmitter

A Low Voltage Differential Signaling (LVDS) compliant receiver includes a differential amplifier having inputs and outputs. A first input coupling capacitor and second input coupling capacitor are electrically coupled to each of the first differential input and the second differential input, respectively. The receiver also includes a first and a second regenerative feedback latching mechanism, and the first regenerative feedback latching mechanism is electrically coupled between the first input coupling capacitor and the first differential output. The second regenerative feedback latching mechanism is electrically coupled between the second input coupling capacitor and the second differential output. An integrated circuit substrate includes each of the differential amplifier, the first differential input, the second differential input, the first differential output, the second differential output, the first regenerative feedback latching apparatus, and the second regenerative feedback latching apparatus are contained thereon. The first and the second input coupling capacitor are on-chip.

Low voltage differential signal receiver with fully integrated AC coupling and bias latching

A digital to analog converter (DAC) includes a quantity of N cells including a Least Significant Bit (LSB) cell, a Most Significant Bit (MSB) cell and, N&#x2212;2 cells ordered therebetween. Each of the N cells is configured to carry a current of I, 2*I, 4*I, 8*I, . . . , 2^(N&#x2212;1)*I, respectively. At least the LSB cell includes a first cell element and a second cell element driven by a first current input and a second current input, respectively. A difference between a magnitude of the first current input and a magnitude of the second input current is approximately equal to I.

High-speed low-latency current-steering DAC

An interleaved digital to analog converter (DAC) includes at least a first signal path and a second signal path. The DAC further includes at least a first high speed DAC and a second high speed DAC each having an input and an output. The first signal path and the second signal path are electrically coupled to the first high speed DAC input and the second high speed DAC input, respectively. The DAC also includes a zero phase clock signal supplied to the first high speed DAC and a 180&#xb0; phase shifted clock signal supplied to the second high speed DAC. A summation circuit, having at least two inputs and one output, is coupled to the outputs of the first high speed DAC and the second high speed DACs. A high-pass delta sigma modulator, a low-pass delta sigma modulator, a band pass delta sigma modulator, or notch filter delta sigma modulator is coupled between the first signal path and the first high speed DAC. A second a high-pass delta sigma modulator, a second low-pass delta sigma modulator, a second band pass delta sigma modulator, or a second notch filter delta sigma modulators electrically coupled between the second signal path and the second high speed DAC.

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Dayton, OH, United States of America

Vipul J Patel