Virage Logic Corporation

Vipin Kumar Tiwari

Jaroslav Raszka

Abhijit Ray

Manish Bhatia

A peak current modeling method and system for modeling peak current demand of an integrated circuit (IC) block such as, e.g., a compilable memory instance. A current demand curve associated with the IC for a particular IC block event is obtained via simulation, for example. A defined time region associated with the particular IC block event is divided into multiple time segments, whereupon at least a first current value and a second current value for each time segment is obtained based on the current demand curve. Thereafter, the current demand curve is approximated, on a segment-by-segment basis, using a select approximate waveform depending on a relationship between the first and second current values.

System and method for peak current modeling for an IC design

A system, method, and computer program product for approximating intrinsic capacitance of an integrated circuit (IC) block such as, for example, a compliable memory instance. Estimates of N-well capacitance, metal grid capacitance, and non-switching circuitry capacitance associated with the IC block are obtained. A total intrinsic capacitance of the IC block is then estimated based on the aforesaid constituent estimates.

System and method for approximating intrinsic capacitance of an IC block

Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

Memory cell sensing with low noise generation

A method and system for storing secure data in a multi-time programmable, non-volatile electrically-alterable memory device are disclosed. Accordingly, in an embodiment, a memory device may include a data register with a fixed N-bit pattern, comparator logic, control logic, and an array of non-volatile electrically-alterable memory cells. Each memory cell includes a floating gate to store an electronic charge representing the logical state of the memory cell. The plurality of memory cells may be logically partitioned to include an N-bit secure lock and a plurality of memory cells for storing secure data. The random bit values stored in the N-bit secure lock are read, and compared with the fixed N-bit pattern stored in the data register. If the N-bit patterns do not match, the control logic allows the plurality of memory cells for storing secure data to be programmed with secure data.

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Fremont, CA, United States of America

Vipin Kumar Tiwari