Micron Technology Incorporated

Intel Corporation

Other

Intel Ndtm US LLC

Violante Moschiano

Giovanni Santin

Tommaso Vali

Andrea D'Alessandro

Michele Incarnati

Kishore Kumar Muchherla

Walter Di Francesco

Akira Goda

Luca De Santis

Paul D Ruby

Umberto Siciliani

Theodore T Pekny

Jeffrey S McNeil, Jr

William Henry Radke

Pranav Kalavade

Walter Di-Francesco

Vishal Sarin

James Fitzpatrick

Michael G Miller

Gary F Besinga

William C Filipiak

Daniel R Elmhurst

Mattia Cichocki

Sivagnanam Parthasarathy

Peter Sean Feeley

Sampath K Ratnam

Patrick Robert Khayat

Giuseppina Puzzilli

Maria-Luisa Gallese

Massimo Rossini

Ashutosh Malshe

Dheeraj Srinivasan

Jae-Kwan Park

Tecla Ghilardi

Andrea Giovanni Xotta

Mason A Jones

Vamsi Pavan Rayaprolu

Bruce A Liikanen

Eric N Lee

Gerald L Cadloni

Luigi Pilolli

Yun Li

Shantanu R Rajwade

Giovanni Naso

Mark A Hawes

Renato Padilla, Jr

Gianfranco Valeri

Paing Z Htet

Frankie F Roohparvar

Harish Reddy Singidi

Renato C Padilla

Emilio Camerlenghi

Ugo Russo

Han Zhao

Allahyar Vahidimowlavi

Purval Shyam Sule

Sead Zildzic, Jr

Ercole Di Iorio

Sead Zildzic

Andrea Smaniotto

Han Liu

Shyam Sunder Raghunathan

Federica Paolini

Jonathan Scott Parry

Mark Alan Helm

Jun Xu

Giulio Giuseppe Marotta

Andrew Bicksler

Marco-Domenico Tiburzi

Erwin E Yu

Raffaele Bufano

Yifen Liu

Jeffrey Scott McNeil, Jr

Tyler L Betz

Mirko Scapin

Yingda Dong

Aaron S Yip

Richard M Fastow

Jung Sheng Hoei

Paolo Tessariol

Abdelhakim Alhussien

Chang Wan Ha

Aliasgar S Madraswala

Tomoko Ogura Iwasaki

Jeremy Binfet

Yogesh B Wakchaure

Phong Sy Nguyen

Ali Mohammadzadeh

Niccolo' Righetti

Carmine Miccoli

Manik Advani

Silvia Beltrami

Christian Caillat

Naveen Kaushik

AbdelHakim S Alhussien

Nagendra Prasad Ganesh Rao

Bharat M Pathak

Maria Luisa Gallese

Naveen Prabhu Vittal Prabhu

A memory device includes a page buffer with multiple registers and a memory array, configured as single-level cell (SLC) memory, including a set of sub-blocks coupled with the page buffer. Control logic is operatively coupled with the page buffer and causes a first page of SLC data to be stored in the multiple registers. The control logic causes a subsequent page of the SLC data to be stored in the multiple registers. The control logic causes the subsequent page and the first page of the SLC data stored in the multiple registers to be concurrently programmed to the set of sub-blocks. The control logic causes at least some of the operations for programming the first page and the subsequent page to the set of sub-blocks to be performed in parallel.

Hybrid parallel programming of single-level cell memory

Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; receiving an actual bit count reflecting a number of memory cells that have their respective threshold voltages below the read level voltage; and responsive to determining that a difference of an expected bit count and the actual bit count exceeds a predetermined threshold value, adjusting the read level voltage.

Validating read level voltage in memory devices

Memories might include a controller configured to cause the memory to prepare a first plurality of memory cells of a block of memory cells for programming from an initialization state of the block of memory cells, program the first data to the first plurality of memory cells, and, in response to receiving a write command associated with a second address corresponding to the block of memory cells and with second data before successfully verifying programming of the first data to the first plurality of memory cells, prepare a second plurality of memory cells of the block of memory cells corresponding to the second address for programming without returning the block of memory cells to the initialization state after programming the first data to the first plurality of memory cells.

Memories for performing successive programming operations

Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array, the block comprising a plurality of wordlines, wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines concurrently and senses a level of current flowing through the sacrificial string while the read voltage is applied. In addition, the control logic identifies, based on the level of current flowing through the sacrificial string, whether a threshold level of read disturb has occurred on the block.

Sacrificial strings in a memory device to detect read disturb

A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.

Shortened single-level cell memory programming

Memory devices and methods for operating the same are described. The memory devices may include non-volatile memory having a plurality of memory cells, and a controller. The controller may be configured to begin a first programming operation configured to program a first one of the plurality of memory cells with more than one bit of information, terminate the first programming operation in response to detecting a power loss event, and program, with a second programming operation, second and third ones of the plurality of memory cells with the more than one bit of information.

Programming operation of memory device being switched from high-density mode to high speed mode and/or lower power mode

A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, determining whether the read operation has failed, in response to determining that the read operation has failed, obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin of a set of state information bins, determining whether to initiate auto-calibrated corrective read, in response to determining to initiate auto-calibrated corrective read, performing read level offset calibration to determine a set of calibrated read level offsets, and causing the set of target cells to be read using the set of calibrated read level offsets.

Auto-calibrated corrective read

A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, obtaining cell state information for each respective group of adjacent cells, for each target cell of the set of target cells, determining a state information bin of a set of state information bins based on the cell state information for its respective group of adjacent cells, and assigning each target cell of the set of target cells to the respective state information bin. Each state information bin of the set of state information bins defines a respective boost voltage level offset to be applied to perform boost voltage modulation.

Boost voltage modulated corrective read

Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.

Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device

An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.

Memory sub-system with dynamic calibration using component-based function(s)

A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

Parallelized defect detection across multiple sub-blocks in a memory device

A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.

Wordline or pillar state detection for faster read access times

A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

Concurrent programming of retired wordline cells with dummy data

The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Determining soft data

A memory device comprising an array of memory cells organized into a set of sub-blocks and a set of wordlines. Control logic is operatively coupled with the array of memory cells, the control logic to perform operations including: receiving a program command from a processing device, the program command including information indicative of a physical address associated with a retired wordline of the set of wordlines; in response to detecting the information within the program command, generating dummy data that is one of pseudo-random data, all one values, or all zero values; and causing the dummy data to be programmed to memory cells of multiple sub-blocks of the set of sub-blocks that are selectively connected to the retired wordline.

Program command generation with dummy data generation at a memory device

Growing community of inventors

Bacoli, Italy

Violante Moschiano