Intel Corporation

Vinu K Elias

Arvind S Tomar

Sundar Ramani

Jianjun Liu

Sridharan Ranganathan

Paul S Durley

Chih-Liang Leon Huang

In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

Autonomously controlling a buffer of a processor

Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.

Methods and systems to measure a signal on an integrated circuit die

Technologies for low-power and high-accuracy timestamps are disclosed. A compute device may have a sensor hub to capture sensor data with a corresponding timestamp. In order to save power, the sensor hub may be able to capture sensor data while the compute device is in a standby mode. However, the always running timer of the compute device may not be accessible to the sensor hub while the compute device is in the standby mode. The sensor hub may have a coarse-grained counter and/or fine-grained counter. To correct for any temporal drift, the compute device may determine an error between the always running timer and the coarse-grained and/or fine-grained counters when the compute device is out of the standby mode, and store an indication of the error in a location accessible by the sensor hub, even when the compute device is in the standby mode.

Technologies for low-power and high-accuracy timestamps

Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal Serial Bus (USB) physical subsystem and system firmware, wherein the system firmware conveys USB related events to the SOC. The system is configured to include a power management apparatus, where the power management apparatus includes USB wake functionality and USB On-the-Go (OTG) functionality.

Block partition to minimize power leakage

Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.

Growing community of inventors

Austin, TX, United States of America

Vinu K Elias