Intel Corporation

Tahoe Research, Ltd.

Other

Vinodh Gopal

Wajdi K Feghali

James D Guilford

Gilbert M Wolrich

Kirk S Yap

Martin Guy Dixon

Erdinc Ozturk

Sean M Gulley

Daniel Cutter

Shay Gueron

Michael E Kounavis

Raghunandan Makaram

Srinivas Chennupaty

Sudhir K Satpathy

Sanu K Mathew

Bret L Toll

Sean Mirkes

Maxim Loktyukhin

Mark C Davis

Alexandre J Farcy

Elmoustapha Ould-Ahmed-Vall

Gunnar Gaubatz

Vikram B Suresh

William C Hasenplaugh

Simon N Peffers

Zeev Sperber

Amit Gradstein

Simon Rubanovich

Ittai Anati

Eric W Mahurin

Jacob Doweck

Jose Yallouz

David L Kreitzer

Regev Shemy

Ilya Albrekht

Robert P Ottavi

Robert Valentine

Mark Jay Charney

Christopher J Hughes

Alexander F Heinecke

Dan Baum

Ronen Zohar

Michael J Espig

Christopher F Clark

Vedvyas Shanbhogue

Jawad Basit Khan

Raanan Sade

Jayesh Gaur

Bradley A Burres

Kahraman D Akdemir

Deniz Karakoyunlu

Akhilesh Thyagaturu

George Powley

Jason W Brandt

Sanjeev N Trika

Mark A Schmisseur

Sreenivas Subramoney

Matthew C Merten

Sivakumar Radhakrishnan

Pierre Laurent

Pankaj Kumar

Sin Sim Tan

Erdine Ozturk

Matt Bace

Ned M Smith

Francesc Guim Bernat

Kshitij Arun Doshi

Ram K Krishnamurthy

Wei Zhang

Peng T Li

Yen-Kuang Chen

Utkarsh Y Kakaiya

Aaron Gorius

Robert S Chappell

Kenneth D Shoemaker

Xiaodong Liu

Tomasz Kantecki

Arun Raghunath

Brent Ralph Boswell

Tracy Garrett Drysdale

Tong Li

Adarsh Chauhan

Kenneth C Haren

Gregory B Tucker

Makaram Raghunandan

John J Vranich

Thomas C Brown

Weigang Li

Olivia Wu

Matthew M Bace

Yogesh Bansal

Rowel S Garcia

James T Kukunas

Andrew Milne

Qihua Dai

Laurent Coquerel

Sejun Kim

Thomas L Dmukauskas

One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand and a second source operand and second circuitry including a processing resource to execute the decoded instruction, wherein responsive to the decoded instruction, the processing resource is to output a result of first source operand data minus second source operand data in response to a determination by the processing resource that the first source operand data is greater than or equal to the second source operand data, otherwise the processing resource is to output the first source operand data.

Conditional modular subtraction instruction

Methods, apparatus, and software for efficient accelerator offload in multi-accelerator frameworks. One multi-accelerator framework employs a compute platform including a plurality of processor cores and a plurality of accelerator devices. An application is executed on a first core and a portion of the application workload is offloaded to a first accelerator device. In connection with moving execution of the application to a second core, a second accelerator devices to be used for the offloaded workload is selected based on core-to-accelerator cost information for the second core. This core-to-accelerator cost information includes core-accelerator cost information for combinations of core-accelerator pairs, which are based, at least on part, on latencies projected for interconnect paths between cores and accelerators. Both single-socket and multi-socket platform are supported. The solutions include mechanisms for moving offloaded workloads for multiple accelerator devices, as well as synchronizing accelerator operations and workflows.

Efficient accelerator offload in multi-accelerator framework

Methods, apparatus, and software for hashing data. The methods and apparatus employ novel improvements to hash algorithms, such as a SHA-2 hash algorithm to reduce computations and increase performance. In one aspect, calculation of SHA-2 message scheduling and SHA compression operations are separated under which an SHA-2 message schedule is applied to multiple rounds of SHA compression operations over multiple chunks of data for the data item being hashed. In another aspect, the SHA-2 message schedule is implemented such that message schedules for multiple message words or data blocks are performed in parallel. The approaches may be employed to reduce hash calculations for various purposes, including generating Filecoin nodes.

Methods and apparatus to hash data

An integrated circuit includes a compression accelerator to process a request from software to compress source data into an output file. The compression accelerator includes early-abort circuitry to provide for early abort of compression operations. In particular, the compression accelerator uses a predetermined sample size to compute an estimated size for a portion of the output file. The sample size specifies how much of the source data is to be analyzed before computing the estimated size. The compression accelerator also determines whether the estimated size reflects an acceptable amount of compression, based on a predetermined early-abort threshold. The compression accelerator aborts the request if the estimated size does not reflect the acceptable amount of compression. The compression accelerator may complete the request if the estimated size reflects the acceptable amount of compression. Other embodiments are described and claimed.

Technology for early abort of compression acceleration

Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

Apparatuses, methods, and systems for hashing instructions

Systems, methods, and apparatuses to low-latency page decompression and compression acceleration are described. In one embodiment, a system on a chip (SoC) includes a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core, cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit, and in response to a second descriptor sent from the hardware processor core separately from the first descriptor, cause the decompressed data to be written from the buffer to memory external to the accelerator circuit by the direct memory access circuit.

Circuitry and methods for low-latency page decompression and compression acceleration

Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Methods, apparatus, and software for efficient encryption in virtual private network (VPN) sessions. A VPN link and an auxiliary link (and associated sessions) are established between computing platforms to support end-to-end communication between respective application running on the platforms. The VPN link may employ a conventional VPN protocol such as TLS or IPsec, while the auxiliary link comprises a NULL encryption VPN tunnel. To transfer data, a determination is made to whether the data are encrypted or non-encrypted. Encrypted data are transferred over the auxiliary link to avoid re-encryption of the data. Non-encrypted are transferred over the VPN link. TLS and IPsec VPN agents may be used to assist in setting up the VPN and auxiliary sessions. The techniques avoid double encryption of VPN traffic, while ensuring that various types of traffic transferred between platforms is encrypted.

Efficient encryption in VPN sessions

Methods and apparatus relating to verifying a compressed stream fused with copy or transform operation(s) are described. In an embodiment, compression logic circuitry compresses input data and stores the compressed data in a temporary buffer. The compression logic circuitry determines a first checksum value corresponding to the compressed data stored in the temporary buffer. Decompression logic circuitry performs a decompress-verify operation and a copy operation. The decompress-verify operation decompresses the compressed data stored in the temporary buffer to determine a second checksum value corresponding to the decompressed data from the temporary buffer. The copy operation transfers the compressed data from the temporary buffer to a destination buffer in response to a match between the first checksum value and the second checksum value. Other embodiments are also disclosed and claimed.

Verifying compressed stream fused with copy or transform operations

Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.

Instruction and micro-architecture support for decompression on core

Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.

Process-based multi-key total memory encryption

Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

Systems and methods for performing matrix compress and decompress instructions

An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.

Compressed cache memory with decompress on fault

Systems, methods, and apparatuses for low-latency page efficient chained decryption and decompression acceleration are described. In one embodiment, a processor comprises a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit to: in response to a descriptor, comprising an indication of a hash key and encrypted data to be decrypted, from the hardware processor core, perform a determination that the encrypted data is to be read in an encrypted order or a reverse order from the encrypted order, in response to the determination that the encrypted data is to be read in the reverse order, generate a resultant authentication tag in the reverse order for the encrypted data based at least in part on the hash key without reordering the encrypted data in the reverse order into the encrypted order, and, in response to the determination that the encrypted data is to be read in the encrypted order, generate the resultant authentication tag in the encrypted order for the encrypted data based at least in part on the hash key.

Circuitry and methods for low-latency efficient chained decryption and decompression acceleration

An apparatus of an aspect includes an encryption unit to receive unencrypted data. The encryption unit is to encrypt the unencrypted data to generate encrypted data. The apparatus also includes circuitry coupled with the encryption unit. The circuitry is to generate a first checksum for a copy of the unencrypted data, generate a second checksum for a copy of the encrypted data, and combine the first and second checksums to generate a first value.

Error resilient cryptographic units and methods

Growing community of inventors

Westborough, MA, United States of America

Vinodh Gopal