International Business Machines Corporation

Vinod Narayanan

Philip S Honsinger

Bruce Martin Fleischer

Terry I Chappell

Barbara A Chappell

David J Widiger

Gary Stephen Ditlow

Barry Lee Dorfman

Michael P Beakes

Ghavam G Shahidi

Robert Alan Philhower

John Youssef Sayah

Shuhui Lin

George Anthony Halasz

Lok T Lui

Lucy Lim

Lok Tin Liu

A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs. The method includes a series of steps that transform a high level design description into a set of SLAMs, and includes the steps of partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure; mapping each logic partition to the target SLAM structure; creating a configuration and relative layout for the internal structure for each SLAM; creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM; assembling the partitions implemented as SLAMs with other macros in the unit; resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs; repeatedly changing the external specifications of the various SLAMs; analyzing the performance of the unit; automatically compiling the schematic and layout of each SLAM within the unit based on the configuration and relative layout; and assembling the macros and analyzing the design for design rule violations.

Method and apparatus for synthesizing and optimizing control logic based

A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems. The distinguishing features of SLAMs are uniquely combined to allow the automated design, from a logic description and interface specifications, of a complete macro satisfying predetermined design guidelines.

Compiled self-resetting CMOS logic array macros

A computer model for facilitating computer assisted design includes data structures which are flexibly organized by storing of information in accordance with entities or simulations thereof (including symbolic layer entities, area entities, area spec entities and area spec usage pattern entities), which are hierarchically associated both by relationships between them at a given level of abstraction of the physical entity they represent and by various attributes that correspond to different levels of abstraction in graphs. The graphs are freely mappable onto any desired fixed data structure such as a hierarchical area tree. Each hierarchical level and particularly the symbolic layer entity within the computer model provides data hiding at each lower level thereof and thus provides data hiding in the fixed data structure by virtue of the mapping function in order to reduce data processing overhead for manipulation of the fixed data structure. Further spatial restriction within one or more symbolic layers is provided by means of an applications window entity. Data compaction is provided by provision of data sharing of area spec entities by plural area entities which are otherwise uniquely maintained.

Hierarchical data model for design automation

A method for assigning interconnection resources to input/output connection points on differential current switch logic elements which need to use the resources, but which introduce an order dependency to the assignment problem, due to restrictions unique to differential current logic. The input/output connection points are paired first as are the interconnection resources. Pairing removes the order dependency. An assignment is then made through the use of an optimizing linear assignment algorithm suitable for single input/output connection point to single interconnection resource assignments. Preferably, a cost matrix is generated to determine the optimum assignment by minimizing the total assignment cost. The paired assignments are then broken apart to assign each individual member of the point pair to an individual member of the assigned resource pair. The final assignment of the individual pair members is compared to legality constraints, the violation of which may have been masked in the calculation of assignment costs of the pairs.

Interconnection resource assignment method for differential current

A wiring methodology for optimizing the wiring of multiple wiring media packages. Data models are created for the package and for the networks which embody the circuit design logic of the package. These data models represent the design data and the contrasting electrical and geometrical characteristics of the different media in a form suitable for the operation of wiring algorithms. In the preferred embodiment, one or more constraint models are associated with each wiring network. The electrical properties and availability limits of all wiring resources are included in the data model. The data model is then used in the selection of a rough path for each connection and the assignment of networks and portions of networks to particular media. The rough path serves as a basis for estimates of the characteristics of the wiring solution for each network. Network assignments and estimates are made globally, considering the information for other networks and package design constraints incorporated into the data model. After assignment of media, networks are partitioned into subconnections. Interface via selection is optimized through a process whereby each possible combination between network pins needing vias and available vias is evaluated with respect to a set of costs. Estimates made in prior steps are used to generate these costs. Following via selection, detail routing can then be implemented by segmenting the wiring problem into separate problems for each medium. These separate problems can be resolved sequentially in no particular order.

Method to optimize the wiring of multiple wiring media packages

A method of assigning pins to corresponding connection points in the design of computer modules where connection points on one layer need to be electrically connected through the pins to a wiring layer so as to minimize the length of the wiring between the points. A best area for selecting a pin is identified for each point that needs to use a pin, and pins are preferentially assigned to the points from their respective best areas. The method introduces a consideration of the direction of the destination point into the assignment solution and allows previous assignment methods to be used which incorrectly assumed that the direction to the destination point could be ignored.

Method for assigning pins to connection points

Growing community of inventors

Fishkill, NY, United States of America

Vinod Narayanan