Xilinx, Inc.

Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Vinod Kumar Kathail

Shail Aditya Gupta

Michael S Schlansker

L James Hwang

Sundararajarao Mohan

B Ramakrishna Rau

Hua Sun

Ralph D Wittig

Philip Bryn James-Roxby

Samuel R Bayliss

Chia-Jui Hsu

Rajiv Gupta

Jorge Ernesto Carrillo

Akella Sastry

Santosh Abraham

Frederic C Amerson

Mukund Sivaraman

Vidhumouli Hunsigida

Robert S Schreiber

Siddharth Rele

Bantwal R Rau

William S Worley, Jr

Yogesh Laxmikant Chobe

Scott A Mahlke

Pradip Jha

Dinesh K Monga

Tom Shui

Rishi Surendran

Vishal Suthar

Srinivas Beeravolu

Ajit K Agarwal

Samuel A Skalicky

Siddarth Rele

Sadun Anik

Greg Snider

Implementing data flows of an application across a memory hierarchy of a data processing array includes receiving a data flow graph specifying an application for execution on the data processing array. A plurality of buffer objects corresponding to a plurality of different levels of the memory hierarchy of the data processing array and an external memory are identified. The plurality of buffer objects specify data flows. Buffer object parameters are determined. The buffer object parameters define properties of the data flows. Data that configures the data processing array to implement the data flows among the plurality of different levels of the memory hierarchy and the external memory is generated based on the plurality of buffer objects and the buffer object parameters.

Implementing data flows of an application across a memory hierarchy of a data processing array

Modeling and compiling tensor processing applications using multi-layer adaptive data flow (ML-ADF) graphs, including folding the ML-ADF graph for temporal sharing of platform resources, computing schedules for runtime orchestration of kernel execution, memory reuse, tensor and sub-volume movement, and dataflow synchronization, and generating binary code for processors of the target computing platform and re-targetable controller code. The ML-ADF graph may represent: tensor processing of a layer of a neural network as data flow through the data nodes and distribution to compute tiles across memory hierarchy; data flow amongst layers of the neural network using connections amongst data nodes of the respective layers; and multi-dimension data partitioning and distribution using tiling parameters associated with ports of the data nodes.

Modeling and compiling tensor processing applications for a computing platform using multi-layer adaptive data flow graphs

Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

Control and reconfiguration of data flow graphs on heterogeneous computing platform

Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices

Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

Dataflow graph programming environment for a heterogenous processing system

For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Hardware-software design flow for heterogeneous and programmable devices

An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Compilation flow for a heterogeneous multi-core architecture

Event tracing for a system-on-chip (SOC) may be implemented by instrumenting, using a computer, a design for the SOC with instrumentation program code that, responsive to execution by a processor of the SOC, generates software trace events. The design may be specified in a high level programming language. A circuit design specifying an accelerator circuit for a function of the design may be generated using the computer. The accelerator circuit is configured for implementation within programmable circuitry of the SOC. The circuit design may be instrumented to include trace circuitry using the computer. The trace circuitry may be configured to detect hardware trace events for operation of the accelerator circuit, receive the software trace events, and combine the hardware and software trace events into time synchronized trace data.

Hardware and software event tracing for a system-on-chip

Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

Encapsulating metadata of a platform for application-specific tailoring and reuse of the platform in an integrated circuit

In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.

Compilation of system designs

Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.

Automatic implementation of a customized system-on-chip

In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.

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Cupertino, CA, United States of America

Vinod Kumar Kathail