Faraday Technology Corporation

Vinod Kumar Jain

Mikhail Tamrazyan

Prateek Kumar Goyal

Chi-Yeu Chao

Han-Kyul Lim

A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.

Wide frequency range burst mode clock and data recovery circuit using clock to data delay compensation method

A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.

CML to CMOS conversion circuit, receiver circuit and conversion method thereof

A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.

Clock and data recovery device with pulse filter and operation method thereof

A serial signal detector and a differential signal detection method are provided. The serial signal detector includes a voltage comparison module and a hybrid logic filter. The voltage comparison module receives a differential signal, including a first shifted signal and a second shifted signal. The voltage comparison module includes a first comparator and a second comparator. Based on the first shifted signal, the second shifted signal, and a voltage threshold, the first and the second comparators respectively generate a first and a second comparison signals. The hybrid logic filter includes a controllable logic gate and a capacitor. The controllable logic gate performs a logic operation related to the first and the second comparison signals and generates a filtered and converted pulse accordingly. The controllable logic gate and the capacitor jointly perform a preliminary filtering operation to the filtered and converted pulse while the logic operation is being performed.

Serial signal detector and differential signal detection method covering multi-protocols

A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.

Clock calibration module, high-speed receiver, and associated calibration method

A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.

Calibration circuit and associated calibrating method capable of precisely adjusting clocks with distorted duty cycles and phases

A signal converter, a duty-cycle corrector, and a differential clock generator are provided. The differential clock generator includes the signal converter and the duty-cycle corrector. The signal converter is capable of calibrating skew distortion, and the duty-cycle corrector is capable of calibrating duty-cycle distortion. With the signal converter and the duty-cycle corrector, the differential clock generator can be applied to communication devices operating at high frequency.

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Hsinchu, Taiwan

Vinod Kumar Jain