Cadence Design Systems, Inc.

Stmicroelectronics International N.v.

General Electric Company

Dell Products Inc.

Emc IP Holding Company LLC

Hewlett Packard Enterprise Development LP

Juniper Networks, Inc.

Emc Corporation

Stmicroelectronics (crolles 2) Sas

Stmicroelectronics Pvt. Ltd.

Tejas Networks Limited

Tangerine Innovation Holding Inc.

The Procter Gamble Company

Vinod Kumar

Hung The Dinh

Thomas Evan Wilson

Saiyid Mohammad Irshad Rizvi

Vinay Sathyanarayana

Abhijit Mishra

Satish Ranjan Das

Hari Anand Ravi

Sachin Ramesh Gugwad

Hajee Mohammed Shuaeb Fazeel

Prakash Kumar Lenka

Tara Vishin

Achalesh Kumar Pandey

Vinay Bhaskar Jammu

Sabu K Syed

Chayan Mitra

Ravi Yoganatha Babu

Panguluru Vijaya Sekhar

Kunal Ravindra Goray

Sheri George

Krishna Mohan Akkinapalli

Reddeppa Kollu

Tousif Mohammed

Jitendra Kumar Yadav

Bhasker Rao Keely

Munish Vishwas Inamdar

Balbeer Rathor

Craig J Van Der Bogart

John Kenneth Maxi

Nagireddy Bonthu

Harsh Anil Shakrani

Mohammed Imran V

Sijoy Thomas

Jeroen Mattijs Van Rotterdam

Sunil Kumar

Bijan Kumar Mohanty

Michael T Mohen

Kallol Chatterjee

David Humby

Shivappa Ningappa Goravar

Paras Garg

Pierre Dautriche

Pankaj Pradhan

Manikandan Pammal Rathinavelu

Ravi Ranjan Jha

Shankar Jayaraman

Gourav Mukherjee

Jatin Kamlesh Thakkar

Anandraj Sengupta

Rohith Vijayakumar Hegde

Aaron Willey

Phalguni Bala

Sudarsanan Codandam

Vellore Mohammed Imran

Naveen Silvester

Karan Kapoor

Chakradhar Kommana

Gnanesh Gowda

Sunija Rishi

Sumit Rishi

Prashant Badaga

Madhusudhana Reddy Chilipi

Pradeep Kumar Badrathwal

SaiyidMohammadIrshad Rizvi

Venkat Allaka

Jyothi K R

Anu Bala Thakur

Mohit Kolluri

Kasnadi Sitaram Nandan

Abhishek Joshi

Subrato Nath

Sujay Prasheel Sundaram

Sarat Manchiraju

Rajashekhar Krishnamurthy Rao

Sumit Gupta

Virvasav Sinha

Puttaraju Bommanna Chikkanna

Gandharva Shankara Murthy

Ayush Kochhar

Krishna Kanth Mallela

Nirmal Jith Oliyil Unnikrishnan

Vineet Kumar

Vijaya Sekhar P

Karishma

Abhinav Srivastava

Roy Niswanger

Naga Hari Prasad Vv Chintakunta

Lakshminarayana Giridhar

A gas turbine engine includes a turbomachine comprising a low pressure (LP) spool and a high pressure (HP) spool that rotate about a central axis, an electric motor mechanically coupled to the LP spool for selectively rotating the LP spool, a starter assembly mechanically coupled to the HP spool for selectively rotating the HP spool, and a controller in operative communication with the electric motor and the starter assembly, the controller being configured to operate the electric motor to rotate the LP spool and operate the starter assembly to rotate the HP spool during engine startup.

Propulsion system including an electric machine for starting a gas turbine engine

Embodiments included herein are directed towards a ring voltage-controlled oscillator based phase locked loop circuit. Embodiments may include an integral path including a plurality of resistors and a plurality of transistors configured to correct low frequency variations and a proportional path in electrical communication with the integral path, the proportional path including a plurality of transistors and a source degeneration circuit. Embodiments may further include a decoupling capacitor located at a ring voltage-controlled oscillator node in electrical communication with the proportional path, wherein the source degeneration circuit operates to cancel any effect from the ring voltage-controlled oscillator node.

Ring voltage controlled oscillator-based phase locked loop with dual charge pump architecture

Embodiments included herein are directed towards a passive equalization circuit. The circuit may include a transmitter, a receiver; and a passive equalization circuit that may be located between the transmitter and the receiver. A first inductor may be located between the transmitter and a primary node net, and a second inductor may be located between the primary node net and a pad, and a third inductor may be located between the primary node net and the receiver.

Passive equalization circuit

Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.

Interface device

Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

Read data strobe path having variation compensation and delay lines

Methods and systems are provided for performing voltage level shifting using thin-oxide devices. The methods and systems convert an input signal associated with a first voltage domain to output signals associated with the first and second voltage domains. A first set of thin-oxide devices generate a first output signal at the high-level voltage signal when the input signal comprises a high logic level and generate the first output signal at a ground level voltage signal when the input signal comprises a low logic level. A second set of thin-oxide devices generate a second output signal at a power supply voltage level of the second voltage domain when the input signal comprises the high logic level and generate the second output signal at the second bias voltage when the input signal comprises the low logic level.

Thin-oxide voltage level shifter

An aircraft includes a gas turbine engine, an electric motor, and a propulsion device. The gas turbine engine and the electric motor are configured to provide a target cumulative output to the propulsion device. An electronic control unit is configured to set the gas turbine engine to a first engine mode to provide a first engine output to the propulsion device, set the electric motor to a first motor mode to provide a first motor output to the propulsion device, a sum of the first engine output and the first motor output being within a predetermined range of the target cumulative output, and in response to a speed of the aircraft reaching a target speed and the first engine output increasing to a second engine output, set the electric motor to a second motor mode.

Aircrafts, systems, and methods for providing constant torque on takeoff

Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a regulated voltage, the regulated voltage having a value proportional to a threshold value associated with a plurality of devices included in the clock distribution path.

Clock distribution architecture

Embodiments included herein are directed towards a transmitter circuit. The circuit may include a most significant bit ('MSB') main driver and a most significant bit boost driver operatively connected to the MSB main driver. The circuit may also include a least significant bit (“LSB”) main driver and a least significant bit boost driver operatively connected to the LSB main driver, wherein the MSB main driver and the LSB main driver are configured to receive two parallel non-return-to-zero (“NRZ”) data inputs.

Transmitter architecture for high speed memory interfaces

Methods, apparatus, and processor-readable storage media for generating data replication configurations using AI techniques are provided herein. An example computer-implemented method includes obtaining input data pertaining to at least one data replication operation; determining a set of configuration parameters for the at least one data replication operation by applying one or more AI techniques to at least a portion of the input data; and performing one or more automated actions based at least in part on the determined set of configuration parameters for the at least one data replication operation.

Generating data replication configurations using artificial intelligence techniques

Various embodiments provide for a data sampler with built-in decision feedback equalization (DFE) and offset cancellation. For some embodiments, two or more data samplers described herein can be used to implement a data signal receiver circuit, which can use those two or more data samplers to facilitate half-rate or quarter-rate data sampling.

Sampler with built-in DFE and offset cancellation

A device, a memory interface device, and a method of implementing an active inductor circuit are disclosed. In one aspect, the device includes one or more active inductor circuits, each including a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a first terminal connected to a first voltage level, a second terminal connected to a resistor, and a gate terminal. The second MOS transistor has a first terminal connected to the first voltage level, a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and a gate terminal connected to the resistor and to a capacitor connected to a second voltage level. One of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is an n-channel MOS (NMOS) transistor.

CMOS active inductor circuit for amplifier

This disclosure relates to slew rate boosting for communication interfaces. A circuit can include a driver circuit coupled to an output node and configured to provide a data signal to the output node based on an input signal. The data signal can a similar logical state as the input signal. The circuit can include a signal transition boosting circuit coupled to the output node and configured to provide a boosting signal to the output node based on the input signal and a charge pump delay adjustment signal. The charge pump delay adjustment signal can define an amount of time after which the boosting signal is provided to the output node. The boosting signal can be provided to the output node to signal boost the data signal for the amount of time defined by the charge pump delay adjustment signal to provide a boosted data signal at the output node.

Slew rate boosting for communication interfaces

The embodiments described herein provide for methods and systems for removing power supply induced jitter from a Phase Lock Loop to provide a Power Supply Induced jitter-free clock signal to a system-on-a-chip and GDDR6 DRAM interface. In operation, a circuit reduces a DC offset between a reference voltage and a voltage regulator output to identify low frequency noise on the voltage regulator output to apply as negative feedback to reduce the low frequency noise on the voltage regulator output. The bandwidth of the circuit is increased to detect high frequency noise, which is applied as negative feedback on the voltage regulator output. Very high frequency noise is then detected and applied as negative feedback to the voltage regulator output. The circuit outputs a regulated output equal to the reference voltage and immune to the low, high, and very high frequency noise of power delivery network supply to the regulator.

High PSR voltage regulator architecture for GDDR6 application

Techniques to determine an execution path in a distributed environment are disclosed. A call to a method or function of a component of the distributed system is received, in connection with a request from a user of the distributed system. A unique correlation identifier that includes data that identifies the component, the request, and the method of function called is generated for the call.

Execution path determination in a distributed environment

Growing community of inventors

Pratapgarh, India

Vinod Kumar