Micron Technology Incorporated

Micron Quantum Devices Inc.

Mosaid Technologies Corporation

Other

Conversant Intellectual Property Management Incorporated

Vinod C Lakhani

Christophe J Chevallier

Robert D Norman

Benjamin S Louie

Mathew L Adsitt

Andrei Mihnea

Tz-Yi Liu

Simon Assouad

Anthony Moschopoulos

Darrell D Rinerson

Darrell D Binerson

A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.

Method for assigning addresses to memory devices

An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

Non-volatile memory devices and control and operation thereof

A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. The new addresses may contain block addresses or block and bank addresses.

Repairable block redundancy scheme

A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.

Column/row redundancy architecture using latches programmed from a look up table

Methods and systems for coupling a laptop or other portable or hand-held device to a docking system using an Ethernet Interface are disclosed and may comprise interfacing a portable computing device to a docking station using an Ethernet interface. Power may be applied from the docking station to the portable computing device via the Ethernet interface using power over Ethernet (POE) protocol. Audio, video, multimedia, control and/or data signals may be communicated between the docking station and the portable computing device via the Ethernet interface. Data exchanged between the portable computing device and the docking station may be encapsulated in Ethernet frames and tagged appropriately. The interface may be accomplished by directly coupling an Ethernet port of the docking station to an Ethernet port of the portable computing device, or by utilizing an Ethernet cable. The docking station may be an active or passive docking station.

Method and system for coupling a laptop or other portable or hand-held device to a docking system using an Ethernet interface

The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.

Method and apparatus for erasing memory

A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a number of modes. In a first mode, high-order address lines select only one block, while in a second mode, user-specified multiple blocks are selected. Blocks are selected by loading registers with selection bits or by using some of the address lines directly as selection bits. Each bit specifies one of the blocks, and each bit is independent of the others. The memory system also includes a predecoder and a controller which controls the predecoder and the registers so as to select at least two blocks of memory cells. In a third mode, all of the blocks are selected, and in a fourth mode, all blocks are deselected. Selecting multiple blocks allows simultaneous erasing, writing, and reading of multiple bytes stored in the memory.

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while minimizing drain voltage induced disturb to cells in unselected erase sectors sharing the same bitlines.

Growing community of inventors

Milpitas, CA, United States of America

Vinod C Lakhani