Marvell International Limited

Vinod Ananth

Bhaskar Chowdhuri

Hongyu Xie

Shui Cheong Lee

Srikanth Shubhakoti

In a media access control (MAC) processor, a programmable controller is configured to execute machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A tightly coupled memory is associated with the programmable controller. A system memory is coupled to the programmable controller via a system bus, and a hardware processor is coupled to the system bus and the tightly coupled memory. The hardware processor is configured to implement MAC functions on data received in a communication frame, store, in the tightly coupled memory, processed data corresponding to data in the communication frame that indicates a structure of downlink data in the communication frame, and store, in the system memory, processed data corresponding to other data in the communication frame.

MAC processor architecture

A media access control (MAC) processor includes a programmable controller and a memory coupled to the programmable controller to store machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A hardware processor is coupled to the programmable controller. The hardware processor includes a processing engine configured to implement MAC functions on the data received by the communication device. The hardware processor additionally includes a context memory coupled to the processing engine to store state information of the processing engine corresponding to one or more contexts, and context switch logic coupled to the processing to determine when the processing engine should switch contexts.

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San Diego, CA, United States of America

Vinod Ananth