Intel Corporation

Vinod Ambrose

Min Huang

Shubhendu Sekhar Mukherjee

Baskaran Ganesan

William Johnson Bowhill

Wayne Burleson

Zhiguo Wang

Eric Dehaemer

Randy L Allmon

Daniel E Holcomb

Joseph R Doucette

Seow Fung Ooi

Jeffrey D Pickholtz

Yin-Lung Lu

Harjinder Hullon

Joseph Doucette

Seow Ooi

In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Apparatus and method to implement power management of a processor

In some embodiments, complementary charge-collecting diffusions (transistor diffusions, e.g., drain or source areas) are disposed close to each other. In some embodiments, dummy ('off') transistors are incorporated to bring complementary diffusions (diffusions of the same charge type and having complementary digital logic levels) closer to each other than otherwise might be possible and thus, to enhance common-mode charge collection for the complementary diffusion areas.

Soft error reduction circuit and method

A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.

Generalized interlocked register cell (GICE)

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Northborough, MA, United States of America

Vinod Ambrose