Micron Technology Incorporated

Vinh Q Diep

Yingda Dong

Ching-Huang Lu

Zhengyi Zhang

Zhenming Zhou

Yu-Chung Lien

Jeffrey Ming-Hung Tsai

Vivek Shivhare

Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

Enhanced gradient seeding scheme during a program operation in a memory sub-system

A memory device comprising a memory array and control logic operatively coupled with the memory array. The control logic is to: detect a program operation directed at a selected wordline of multiple wordlines of the memory array; determine, during an initial phase of the program operation, whether a program voltage being applied to the selected wordline satisfies a threshold program voltage; add, in response to the program voltage not satisfying the threshold program voltage, a base offset voltage to an initial pass voltage to generate a higher pass voltage, the initial pass voltage being a percentage of an initial program voltage; and cause the higher pass voltage to be applied to a remainder of the multiple wordlines other than the selected wordline.

Selective increase and decrease to pass voltages for programming a memory device

Methods, systems, and apparatuses include determining an operation type for an operation. A sensing time is elected using the operation type. The operation is executed using the sensing time.

Adaptive sensing time for memory operations

Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

Bias voltage schemes during pre-programming and programming phases

Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

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Hayward, CA, United States of America

Vinh Q Diep