Lsi Corporation

Vineet Sreekumar

Ramesh C Tekumalla

Prakash Krishnamoorthy

Niranjan Anant Pol

Suharli Tedja

James G Monthie

Ranjit Yashwante

Swarupchandra Kamerkar

Yadvinder Singh

An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed to enable customization of the current-demand characteristics exhibited by the integrated circuit, e.g., based on the circuit's spectral impedance profile, to cause transient voltage droops in the power-supply network of the integrated circuit to be sufficiently small to ensure proper and reliable operation of the integrated circuit.

Programmable clock spreading

First and second apparent resistance measures are determined for an integrated circuit and utilized to characterize the integrated circuit. The first apparent resistance measure is determined for the integrated circuit based on a first voltage drop and a first current that are measured using test equipment. The second apparent resistance measure is determined for the integrated circuit based on a second voltage drop and a second current that are obtained using static analysis of a corresponding integrated circuit design. The integrated circuit is characterized based on a comparison of the first and second apparent resistance measures. For example, characterizing the integrated circuit may comprise validating the static analysis of the integrated circuit design based on the comparison of the first and second apparent resistance measures, or determining a quality measure of the integrated circuit based on the comparison of the first and second apparent resistance measures.

Integrated circuit characterization based on measured and static apparent resistances

An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller.

Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain

Growing community of inventors

Mumbai, India

Vineet Sreekumar