Synopsys, Inc.

Cisco Technology, Inc.

Vineet Gupta

Akash Renukadas Deshpande

Roberto Attias

Shobhit Sonakiya

Navendu Sinha

Stephen John Joseph Fricke

William Charles Jordan

Bryon Irwin Moyer

Timothy Peter Stammers

Arghya T Mukherjee

Kaushik L Popat

Thomas Pennello

Suvitha Kesavan

Amarnath Sury Arvind

Purval Prakash Shah

Rutuja Ravindra Shivde

Gopal Pralhadrao Jorapur

Jinpei Qiang

Martin Kite

Lakshmi Thiyagarajan

Nicholas Butler

In one embodiment, a device receives data regarding a node from a plurality of management platforms, each management platform being associated with a different access network used by the node. The device applies a unified data model to the data regarding the node received from the plurality of management platforms, to form unified data regarding the node. The device analyzes the unified data regarding the node, to generate insight information. The device provides the insight information to an application associated with a manufacturer of the node.

Unified management and monitoring of IoT nodes with multiple network connections

Systems and methods provide for network-initiated recovery from a failure during transmission of text messages (e.g., Short Message Service or SMS) sent from circuit-switched (CS)/packet-switched (PS) infrastructure to a Mobile Station or User Equipment (MS/UE) connected to a PS radio access network. A text message service center (e.g., SMS Center or SMSC) can receive a message destined for the MS/UE. The SMSC can request from a home location register (HLR) routing information to a first text message interworking function (e.g., SMS-IWF) associated with a first visitor location register (VLR). The SMSC can receive data indicating that the first SMS-IWF/VLR is unreachable. The SMSC can transmit to the HLR an indication of an absent subscriber causing the HLR to request a Mobility Management Entity (MME) to reattach the MS/UE to a second SMS-IWF/VLR. In some embodiments, the MS/UE may reattach only to the second SMS-IWF/VLR (e.g., instead of a full reattach).

Network-initiated recovery from a text message delivery failure

System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

Hardware accelerator test harness generation

A memory management unit (MMU) is disclosed for storing mappings between virtual addresses and physical addresses. The MMU includes a translation look-aside buffer (TLB) and a memory management unit controller. The TLB stores mappings between a virtual address and a physical address. The MMU controller receives a request to insert an entry into the TLB and performs a set of operations based on the received request. The MMU controller determines whether an entry stored in the TLB is associated with the virtual address of the request, removes the entry stored in the TLB that is associated with the virtual address and inserts the requested entry into the TLB.

Method and processor for reducing code and latency of TLB maintenance operations in a configurable processor

Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.

Structured block transfer module, system architecture, and method for transferring

Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host., the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.

A system and a method are disclosed for more efficiently handling shared code stored in memory, comprising a modified memory management unit containing a new shared address space identifier register, and a modified TLB entry containing a new shared bit.

Extending processor MMU for shared address spaces

Generating hardware accelerators and processor offloads

Packet ingress/egress block and logic and system and method for receiving, transmitting, and managing packetized data. System including a line port; a computing resource output port; a host interface; a memory, and a block that: receives information on the line port, creates a context including information for managing computation derived from the received information, and sends context out on computing resource output port. Device comprising first circuit component including line port that receives information, second circuit component that generates context information including an information for managing computation derived from the received unit of information; and third circuit component that communicates the generated context out to a computing resource output port. Method comprising receiving information, generating context information including an information for managing computation derived from the received unit of information; and communicating the generated context information out to an external receiver via a computing resource output port.

Growing community of inventors

San Jose, CA, United States of America

Vineet Gupta