Qualcomm Incorporated

Advanced Micro Devices Corporation

Lsi Logic Corporation

Ati Technologies Inc.

Cisco Technology, Inc.

Juniper Networks, Inc.

Ati Technologies Ulc

Ati International Srl

Intel Corporation

Vineet Goel

Usame Ceylan

Todd Martin

Andrew Evan Gruber

Skyler Jonathon Saleh

Mangesh P Nijasure

Donghyun Kim

Swapnil Pradipkumar Sakharshete

Ruijin Wu

Young In Yeo

Anirudh Rajendra Acharya

Jason David Carroll

Juraj Obert

Christopher Jude Brennan

Maxim V Kazakov

Michael Mantor

Tao Wang

Gang Zhong

Robert Scott Hartog

Andrew S Pomianowski

Pazhani Pillai

Chunhui Mei

Milind Nilkanth Nemlekar

Nariman Moezzi Madani

Stephen L Morein

Alexei Vladimirovich Bourd

Bruno Rijsman

Aseem Asthana

Jay Chunsup Yun

Liang Li

Leonardo Vainsencher

Jian Mao

Brian A Buchner

Subbu Subramaniam

Sunil Bakhru

Kallol Banerjee

Alexander M Potapov

Ranadip Das

Javier Ignacio Girado

Ouns Mouri

Ranjini Rajendran

Alexander C Vlachos

Nathaniel H Ingersoll

Yan Li

Guofang Jiao

Val Gene Cook

Jian Long Yang

Sravan Vadlakonda

Mika Tuomi

Michael Andrew Mang

Manjunath Sreedhara Bangalore

Ashish P Chotai

Kiia Kaappoo Kallio

David Rigel Garcia Garcia

Ralph Clayton Taylor

Maurice Franklin Ribble

Elina Kamenetskaya

Sagar Shankar Bhandare

Binh Don Ha

Samuel Lawrence Wasmundt

Martin G Sarov

Stuart Krupnik

Huaibing Zhu

Connie Tang

Nishit Kumar

Ashish Chotai

A device is disclosed. The device includes a machine learning die including a memory and one or more machine learning accelerators; and a processing core die stacked with the machine learning die, the processing core die being configured to execute shader programs for controlling operations on the machine learning die, wherein the memory is configurable as either or both of a cache and a directly accessible memory.

Stacked dies for machine learning accelerator

A graphics processing unit (GPU) for clustering of machine learning (ML) functional components, including: a plurality of compute units; a plurality of ML clusters, wherein each of the ML clusters comprises at least one arithmetic logic unit (ALU), and wherein each of the ML clusters is associated with a respective subset of the compute units; and a plurality of memory modules each positioned on the GPU adjacent to a respective ML cluster of the plurality of ML clusters, wherein each ML cluster is configured to directly access one or more adjacent memory modules.

Clustering of machine learning (ML) functional components

Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

Patched shading in graphics processing

Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading ('VRS') data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.

VRS rate feedback

A processing device and a method of tiled rendering of an image for display is provided. The processing device includes memory and a processor. The processor is configured to receive the image comprising one or more three dimensional (3D) objects, divide the image into tiles, execute coarse level tiling for the tiles of the image and execute fine level tiling for the tiles of the image. The processing device also includes same fixed function hardware used to execute the coarse level tiling and the fine level tiling. The processor is also configured to determine visibility information for a first one of the tiles. The visibility information is divided into draw call visibility information and triangle visibility information for each remaining tile of the image.

Hybrid binning

A processing device is provided which includes memory and a processor. The processor is configured to receive an input image having a first resolution, generate at least one linear down-sampled version of the input image via a linear upscaling network, generate at least one non-linear down-sampled version of the input image via a non-linear upscaling network, extract a first feature map from the at least one linear down-sampled version of the input image, and extract a second feature map from the at least one non-linear down-sampled version of the input image. The processor is also configured to convert the at least one linear down-sampled version of the input image and the at least one non-linear down-sampled version of the input image into pixels of an output image having a second resolution higher than the first resolution using the first feature map and the second feature map.

Gaming super resolution

A processing device is provided which includes memory configured to store data and a processor configured to determine, based on convolutional parameters associated with an image, a virtual general matrix-matrix multiplication (GEMM) space of a virtual GEMM space output matrix and generate, in the virtual GEMM space output matrix, a convolution result by matrix multiplying the data corresponding to a virtual GEMM space input matrix with the data corresponding to a virtual GEMM space filter matrix. The processing device also includes convolutional mapping hardware configured to map, based on the convolutional parameters, positions of the virtual GEMM space input matrix to positions of an image space of the image.

Hardware accelerated convolution

A processing device is provided which includes memory and a processor. The processor is configured to receive an input image having a first resolution, generate linear down-sampled versions of the input image by down-sampling the input image via a linear upscaling network and generate non-linear down-sampled versions of the input image by down-sampling the input image via a non-linear upscaling network. The processor is also configured to convert the down-sampled versions of the input image into pixels of an output image having a second resolution higher than the first resolution and provide the output image for display.

A texture processor based ray tracing accelerator method and system are described. The system includes a shader, texture processor (TP) and cache, which are interconnected. The TP includes a texture address unit (TA), a texture cache processor (TCP), a filter pipeline unit and a ray intersection engine. The shader sends a texture instruction which contains ray data and a pointer to a bounded volume hierarchy (BVH) node to the TA. The TCP uses an address provided by the TA to fetch BVH node data from the cache. The ray intersection engine performs ray-BVH node type intersection testing using the ray data and the BVH node data. The intersection testing results and indications for BVH traversal are returned to the shader via a texture data return path. The shader reviews the intersection results and the indications to decide how to traverse to the next BVH node.

Texture processor based ray tracing acceleration method and system

Described herein are techniques for improving the effectiveness of depth culling. In a first technique, a binner is used to sort primitives into depth bins. Each depth bin covers a range of depths. The binner transmits the depth bins to the screen space pipeline for processing in near-to-far order. Processing the near bins first results in the depth buffer being updated, allowing fragments for the primitives in the farther bins to be culled more aggressively than if the depth binning did not occur. In a second technique, a buffer is used to initiate two-pass processing through the screen space pipeline. In the first pass, primitives are sent down to update the depth block and are then culled. The fragments are processed normally in the second pass, with the benefit of the updated depth values.

Method and system for depth pre-processing and geometry sorting using binning hardware

Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading ('VRS') data, updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data, and writing a VRS rate feedback buffer based on the updated VRS data.

A compute unit accesses a chunk of bits that represent indices of vertices of a graphics primitive. The compute unit sets values of a first bit to indicate whether the chunk is monotonic or ordinary, second bits to define an offset that is determined based on values of indices in the chunk, and sets of third bits that determine values of the indices in the chunk based on the offset defined by the second bits. The compute unit writes a compressed chunk represented by the first bit, the second bits, and the sets of third bits to a memory. The compressed chunk is decompressed and the decompressed indices are written to an index buffer. In some embodiments, the indices are decompressed based on metadata that includes offsets that are determined based on values of the indices and bitfields that indicate characteristics of the indices.

Compression and decompression of indices in a graphics pipeline

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Winter Park, FL, United States of America

Vineet Goel