Advanced Micro Devices Corporation

Vineet Dujari

Nicos S Syrimis

Mark S Young

Michael C Shebanow

John Drew

Larry A Copp

Douglas G Gray

An error processor on a single integrated circuit chip to detect and correct errors in a block of received data. The error processor includes processing hardware for receiving data and for generating syndrome bytes corresponding to the received data. It also includes processing hardware for detecting errors in the received data and for generating correction vectors to indicate the relative locations and error values thereof. An interface is connected to the processing hardware for facilitating data transfer to and from a communications bus.

Single chip error processor

A buffer memory subsystem for a peripheral controller. A CPU is provided for initiating data transfer. A host adapter is also provided. A memory buffer is used to store data temporarily. The peripheral controller is adapted for operating in an environment having at least two data communications buses: a CPU data communications bus connected between the CPU and the peripheral controller, and a buffer data communications bus, isolated from the CPU data communications bus, and connected to the peripheral controller, to the memory buffer and to the host adapter. In this way, a mechanism is provided to allow the CPU to access the memory buffer by means of the peripheral controller.

Buffer memory subsystem for peripheral controllers

A system for transferring the status information between a peripheral controller and central processing unit (CPU) is disclosed. The system utilizes three registers and an interrupt pin for determination of the presence of a STATUS VALID bit. If the STATUS VALID bit is set, then a STATUS OVERFLOW bit is set by the peripheral controller. If the STATUS VALID bit is not set, the peripheral controller updates the status information and sets the STATUS VALID bit. Through the use of this transfer system much of the complexity associated with known systems is eliminated without the concomitant loss in processing speed.

Status transfer structure within a data processing system with status

A method of transferring data in one access cycle between two devices over a communications bus. Data is read from a predetermined location in the first device. The data is also latched into a temporary register. Data is simultaneously written into a predetermined location of a second device. The read operation of the first device is terminated and the data from the temporary register is applied to the second device simultaneously with the termination step so that data is available to the second device notwithstanding the fact that the first device has ceased transmission.

Fly-by data transfer system

A flexible, sequencer for providing next-address generation in the execution of a microprogram is described. The sequencer includes means for receiving an externally provided base address and an externally provided address offset value, a stack for storing return base address pointers, and means for storing a current program pointer counter address. The sequencer comprises means for selecting an address from one of a plurality of generated addresses and for providing the selected address as the next address in the execution of the microprogram, and means for generating the plurality of addresses including an address generation means selected from the group consisting of means for adding the address offset value with a stack stored return base address, means for adding the address offset value with the current program pointer counter address, means for selectively incrementing the selected address by one of a plurality of predetermined integral values, and means for selectively shifting the address offset value and for overlaying the external base address with the shifted address offset value, each means respectively generating one of the plurality of the generated addresses.

Flexible, next-address generation microprogram sequencer

A novel technique for skipping defects on a magnetic or writable optical disk is described. The technique includes a sector format comprising a header (24) and data area (28), wherein the data area can include one or more 'bad areas' (108, 116) which will be skipped when data is being written to or read from the sector. The bad areas are variable in size and may be located anywhere in the data area, including in an EDAC. The header includes a defect descriptor (48) comprising a defect pointer (70, 72) for each of the bad areas supported. Each defect pointer contains a value (74, 78) indicating the number of bytes in the good data area (106, 114) preceding the bad area pointed to by the defect pointer, and a value (76, 80) indicating the number of bytes in the bad area. The value indicating the number of bytes in a good area is set to a value indicating a number of bytes at least as large as the sector size if there is no subsequent bad area in the data area.

Defect skipping mechanism for disk drives

A method and apparatus for reading data from a disk having missing or unreadable field address marks. Expected address marks are searched for within a time window which is generated using a counter. When an expected address mark is generated at any time within the time window, the counter is set or reset to generate another time window within which the next address mark is expected to occur. By starting or restarting the counter each time an expected address mark is detected the effects of variations in spindle speed which occur prior to the detection of the address mark are eliminated, thus increasing the probability that readable address marks will be detected within a time window.

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Santa Clara, CA, United States of America

Vineet Dujari