Ams Ag

Ams International Ag

Austriamicrosystems Ag

Vincenzo Leonardo

Mark Niederberger

Camillo Stefanucci

Srinidhi Koushik Kanagal Ramesh

A circuit arrangement is provided where the arrangement of a feedback resistor between a first branch and a second branch enables that a voltage is provided at an output terminal in an efficient way, this means with a high settling speed and a low current consumption. The feedback resistor is arranged between a reference node and the output terminal, where the reference node is connected to a current mirror. The circuit arrangement can be employed as a gate driver. Furthermore, a driver block and a method of driving a circuit arrangement are provided.

Circuit arrangement for a gate drive with a feedback resistor

A comparator circuit includes an input stage with a set of differential current paths and a pair of differential input transistors connected to a pair of input terminals. An output stage includes an output current path between a first and a second supply terminal, an output transistor connected in the output current path and having a control terminal coupled to the set of differential current paths, and a comparator output connected to the output current path. An auxiliary stage includes an auxiliary current path between the supply terminals, an auxiliary current source, a first auxiliary transistor connected in the auxiliary current path and having a control terminal connected to the control terminal of the output transistor, and a voltage follower with a second auxiliary transistor and a third auxiliary transistor. The second auxiliary transistor controls the voltage follower and the third auxiliary transistor couples the control terminal of the output transistor to at least one of the set of differential current paths.

Comparator circuit

A power on reset circuit comprises terminals for reference and supply potentials and a voltage divider coupled therebetween. First and second transistors of a bandgap circuit are resistively coupled to the reference potential terminal and have bases connected to the voltage divider. Current mirrors couple the collectors of the first and second transistors to an output terminal providing an output signal indicating a power on reset condition. A first compensation transistor is coupled between the collector of one of the transistors and the reference potential terminal, and a second compensation transistor is coupled between the output terminal and the reference potential terminal to compensate the effect of parasitic substrate currents in response to an external interference.

Power on reset circuit and integrated circuit including the same

An output driver () comprises a driver transistor (MP) having a gate node (GMP) to apply a gate control voltage (GCV) and a gate control circuit () to control the gate node (GMP) of the driver transistor (MP). The output driver () is configured to be operable in a first operation mode and a second operation mode, the variable resistance of the current path of the driver transistor (MP) being lower in the first operation mode than in the second operation mode. The gate control circuit () comprises a controllable resistor (RC), the controllable resistor (RC) being disposed between the gate node (GMP) of the driver transistor (MP) and an output node (QP) of the output driver (), and a resistance of the controllable resistor (RC) being dependent on operating the output driver in the first or second operation mode.

Output driver with reverse current blocking capabilities

A high-voltage output driver () for a sensor device () with reverse current blocking comprises a supply node (SN) to apply a supply voltage (VHV) and an output node (OP) to provide an output signal (OS) of the high-voltage output driver (). The high-voltage output driver () comprises a driver transistor (MP) being disposed between the supply node (SN) and the output node (OP). The high-voltage output driver () further comprises a bulk control circuit () to apply a bulk control voltage (Vwell) to a bulk node (BMP) of the driver transistor (MP), and a gate control circuit () to apply a gate control voltage (GCV) to the gate node (GMP) of the driver transistor (MP).

High-voltage output driver for a sensor device with reverse current blocking

An amplifier arrangement comprises a sensor input and a first and a second amplifier. The first amplifier has a first amplifier output and a first input connected to a first reference potential terminal and a second input connected to the sensor input in a direct fashion and to the first amplifier output via a feedback path having a switched integration capacitor that is charged by the feedback path during a first switching phase and discharged during a second switching phase. The second amplifier has a second amplifier output, a first input connected to a second reference potential terminal and a second input. A first feedback capacitor is connected in-between two pairs of feedback switches. A second feedback capacitor is connected between the second amplifier output and the second input of the second amplifier. An impedance element is coupled between the second amplifier output and the sensor input.

Amplifier arrangement and sensor arrangement with such amplifier arrangement

An avalanche diode arrangement () comprises an avalanche diode () that is coupled to a first voltage terminal () and to a first node (), an event detector () for detecting a trigger event of the avalanche diode () and being coupled to the first node (), a quenching circuit () that is coupled to the first node (), and a detection circuit () coupled to the first node (). The detection circuit () is configured to provide a detection signal (SVC) that depends on a value of a node voltage (SVA) at the first node ().

Avalanche diode arrangement and method for providing a detection signal

A detection circuit has a detection path and a control path. The detection path comprises a signal limiter () with a signal input (), which is connected to a detection node (OUT), and a filter () which is coupled to a signal output () of the signal limiter (). The detection path also comprises a short circuit detector () with a first and a second detector input () and a detector output (), wherein the first detector input () is coupled to the filter (). The control path comprises a control circuit () for controlling a switch () which is coupled to the detector output () and to the filter () by means of a control input () and is connected to the switch () by means of a control output (). The switch () is coupled to the detection node (OUT) and to a supply node (VSS, VHV).

Detection circuit and method for operating a detection circuit

An amplifier circuit comprises a measurement path with an amplifier () for providing an output voltage (Vout) depending on a measuring current (Ipd) with a first and a second amplifier input (), and an amplifier output (). A return path of the amplifier circuit comprises a first filter (), an auxiliary amplifier () and a second filter (). In this case, the first filter () is designed to filter a DC voltage from the output voltage (Vout) and is connected to the amplifier output (). The auxiliary amplifier () serves to convert an input voltage (Vfil) into an output current (Ifil) and has a first and a second auxiliary amplifier input () and an auxiliary amplifier output (). In this case, the first auxiliary amplifier input () is connected to the first filter (). The second filter () is designed to filter noise from the output current (Ifil) and couples the auxiliary amplifier output () to the first amplifier input ().

Amplifier circuit, detector arrangement and method for operating an amplifier

A method for offset compensation of a switched-capacitor amplifier comprises a reset phase (&#x3c6;) and at least one working phase (&#x3c6;). An output voltage (Vout) of the amplifier (amp) is fed according to a damped feedback loop gain (AB()) to a first amplifier input (ain) in the reset phase (&#x3c6;) as a function of an offset voltage (Voff). In the least one working phase (&#x3c6;), an offset of the amplifier (amp) is compensated as a function of the offset voltage (Voff) by superimposing the output voltage (Vout) onto an input voltage (Vin) of the amplifier (amp) according to a loop gain (AB()).

Method for offset compensation of a switched-capacitor amplifier and switched capacitor amplifier arrangement

A circuit arrangement for shifting a voltage level comprises a data-current converter () that is connected to a first connection (K) and that has an input for feeding a digital input data signal (DIN), a first output for providing a current (I), and also a second output for providing a reference current (I), and a current-data converter () that is connected to a second connection (K) and that has a first input for feeding the current (I), a second input for feeding the reference current (I), and also an output for providing a digital output data signal (DOUT). Here, a voltage level of the digital output data signal (DOUT) is different from a voltage level of the digital input data signal (DIN). In addition, a method for shifting a voltage level is provided.

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Wadenswil, Switzerland

Vincenzo Leonardo