Stmicroelectronics S.r.l.

Vincenzo Dima

Lorenzo Bedarida

Simone Bartoli

Nicola Del Gatto

Antonino Geraci

Emanuele Confalonieri

Mauro Luigi Sali

Carlo Lisi

Marco Defendi

Carla Giuseppina Poidomani

Antonio Geraci

Carmelo Chiavetta

Fabio Disegni

Francesco Brani

A method for management of the programming controls in a multilevel device is provided. During the control step cells are not controlled all together but they are conveniently selected in order to reduce the source resistance and consumption effect, but without penalizing change times.

Programming method for non volatile multilevel memory cells and corresponding programming circuit

A voltage regulator with quick response includes: an output terminal supplying a regulated voltage; and at least a first boost circuit, controlled for alternately accumulating a first charge in a first operating condition and supplying the first charge to the output terminal in a second operating condition. In addition, the first boost circuit is provided with a compensation stage supplying the output terminal with a second charge substantially equal to the first charge, when the first boost circuit is in the first operating condition.

Voltage regulator with very quick response

A circuit design of a transistor connected as a diode, in particular to a design able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. The circuit design includes a first pMOS transistor having a second nMOS transistor connected as a diode connected between the gate and the drain of the first transistor and a current generator connected to the gates of the two transistors. Such a circuit design is also applicable to a nMOS transistor. From a general point of view the invention is directed to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series with the gate that provides an appropriate delta of voltage. 3)

Threshold voltage reduction of a transistor connected as a diode

The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

Circuit arrangement for the lowering of the threshold voltage of a diode configured transistor

A memory device comprises a plurality of independent memory sectors, external address signal inputs for receiving external address signals that address individual memory locations of the memory device, the external address signals including external memory sector address signals allowing for individually addressing each memory sector, and a memory sector selection circuit for selecting one of the plurality of memory sectors according to a value of the external memory sector address signals. A first and a second alternative internal memory sector address signal paths are provided for supplying the external memory sector address signals to the memory sector selection circuit, the first path providing no logic inversion and the second path providing logic inversion. A programmable circuit activates either one or the other of the first and second internal memory sector address signal paths, so that a position of each memory sector in a space of values (00000h-3FFFFh) of the external address signals can be changed by activating either one or the other of the first and second internal memory sector address signal paths.

Sectored semiconductor memory device with configurable memory sector addresses

A circuit for reading a semiconductor memory device includes at least one global circuit for generating a global reference signal for a respective plurality of cell-reading circuits disposed locally in the memory device. The circuit includes at least one circuit for replicating the reference signal locally in order to generate a local reference signal to be supplied to at least one respective cell-reading circuit.

Circuit for reading a semiconductor memory

An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

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Monza, Italy

Vincenzo Dima