Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Vincent Yin

Liang Li

Xuan Tian

Dandan Yi

Jojo Xing

Jiahui Yuan

Henry Chin

Alan David Bennett

Wei Zhao

Yongke Sun

Tony Zou

A non-volatile storage apparatus comprises memory cells organized into multiple planes. To prevent one plane from disturbing another plane while concurrently programming memory cells in a first plane and memory cells in a second plane, the system determines that the memory cells in the second plane are programming slower than the memory cells of the first plane, tests whether the memory cells in the first plane have threshold voltages greater than a test level that is higher than a target verify level, determines that the memory cells in the first plane failed programming if more than a maximum number of the memory cells in the first plane have threshold voltages greater than the test level, and determines that the memory cells in the second plane failed programming if not more than a maximum number of the memory cells of the fast plane have threshold voltages greater than the test level.

Non-volatile memory with enhanced early program termination mode for neighbor plane disturb

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in memory holes. The memory holes are arranged in rows comprising strings which are grouped into blocks comprising a first plane and a second plane. A control means is configured to program memory cells of the first plane and the second plane connected to one of the word lines using iterations of a program operation. The control means terminates programming of the first plane prior to completing programming of the first plane in response to determining the first plane programs slower than the second plane by a predetermined number of the iterations of the program operation. The control means adjusts the predetermined number of the iterations based on an additional verify iteration performed on at least some of the memory cells beyond the iterations of the program operation.

Smart early program termination algorithm for neighbor plane disturb countermeasure

In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.

Non-volatile memory with layout adaptive problematic word line detection

In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.

Storage system and method for proactive die retirement by fatal wordline leakage detection

The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

Techniques for checking vulnerability to cross-temperature read errors in a memory device

Apparatuses and techniques are described for recovering from errors in a read operation. When a read operation results in an uncorrectable read error, recovery read operations are performed for each read voltage of a page of data. Each recovery read operation uses a different timing. The different timings can involve a time period which is allocated for a voltage transition, such as a settling time of a word line or bit line voltage, or a time allocated for an under kick or over kick of a word line or bit line voltage. An error count is obtained for each different timing, and an optimum timing is determined based on the lowest error count. A retry read operation is performed in which an optimum timing is used for the voltage transition for each read voltage of the page.

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Shanghai, China

Vincent Yin