Xilinx, Inc.

Vincent Vendramini

Matthew H Klein

David Taylor

In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.

Latency control in a transmitter/receiver buffer

An embodiment of an apparatus includes a detector to receive a first input signal and a second input signal to provide a first error signal and a second error signal. A pulse width determination block receives the first and second error signals, as well as a digital oscillating signal, to output a first pulse width value and a second pulse width value, respectively. A pulse width accumulator accumulates the first and second pulse width values responsive to at least one cycle of the digital oscillating signal to provide a first accumulated value and a second accumulated value. An error generator provides an error value as a difference between the first accumulated value and the second accumulated value. The error value represents a pulse width difference between the first input signal and the second input signal indicative of a phase difference between the first input signal and the second input signal.

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Dublin, Ireland

Vincent Vendramini