International Business Machines Corporation

Stmicroelectronics S.a.

Mentor Graphics Corporation

Vincent Vallet

Philippe Hauviller

Dominique P Bonneau

Patrick Mone

Myriam Combes

Carl Cederbaum

Roland Chanclou

Didier Malcavet

Anna Asquini

Philippe Hanviller

A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Duty cycle protection circuit

An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or transitions). The incoming serial data stream with jitter is oversampled in an oversampling circuit by means of the multiple phases of a reference clock (clk) to produce data samples. Each sample is compared to the sample(s) collected with the next clock phase(s) in an edge detector circuit to determine the presence of a data edge and the edge information is stored and accumulated in a data edge memory. A selection determination circuit uses the memorized edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Data recovery circuits using oversampling for best data sample selection

Disclosed herein is an improved serializer/deserializer (SERDES) circuit () having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (). To that end, a delay perturbation is added to the serial data stream at the serializer () output, typically using a variable delay (DEL) line (). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic () coupled to the DEL line and the deserializer circuit () analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Characterizing jitter sensitivity of a serializer/deserializer circuit

Serializer/deserializer circuit for jitter sensitivity characterization

A data recovery circuit employing an oversampling technique. The incoming serial data stream with jitter is oversampled by means of the multiple phases of a reference clock to produce data samples. Each sample is compared to the samples collected with the next clock phase in an edge detector circuit to determine the presence of a data edge. The edge information, representative of the data edge positions, is stored and accumulated in the form of a bit map. A detection/suppression circuit detects and suppresses edges which are not adjacent to any other edge in the edge memory. A selection determination circuit uses the edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Data recovery circuits using oversampling for maverick edge detection/suppression

A transition detection, validation and memorization (TDVM) circuit detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. Then n over sampled signals are fed into the TDVM circuit which includes a first section for detecting the transition at the positions of two consecutive sampled signals according to a specific signal processing, a second section for validating the transition position, and a third section for memorizing the validated transition position and generating a control signal that is used to recover the data.

Transition detection, validation and memorization circuit

There is disclosed a data recovery (DR) circuit including an over sampling (OS) circuit, a transition detection (TD) circuit and a sample selection/data alignment (SSDA) circuit. A multiphase clock generating circuit delivering n phases is coupled to each of these circuits. The OS circuit over samples the received digital data stream and produces n sampled signals at each clock period. The TD circuit is configured to detect a data transition (if any) and to generate n select signals, only one of which is active and represents a determined delay with respect to the transition position, indicating thereby which over sampled signal is the best to be retained. The SSDA circuit is configured to generate the recovered (retimed) data signal that is aligned with a predefined phase of the multiphase clock signal. The data recovery circuit is well adapted to high speed serial data communications between integrated circuits/systems on digital networks.

Method and circuit for recovering a data signal from a stream of binary data

There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G, . . . , G) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G, . . . , G) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G, . . . , G) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.

Sample selection and data alignment circuit

A built-in self test system for testing a clock and data recovery circuit. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.

Built-in self test system and method for high speed clock and data recovery circuit

The present invention provides an apparatus for setting the free-running frequency of a VCO to a reference frequency. The apparatus comprises frequency range means for setting the VCO within a VCO frequency range among a plurality of VCO frequency ranges. First counting means are operable to count to a first value at the VCO frequency rate and to provide a first ending signal when the first value is reached. Second counting means are operable to count to a second value at the reference frequency rate and to provide a second ending signal when the second value is reached. The second counting means are also operable to provide a reference count value when the first value is reached by the first counting means. A state machine is responsive to the first and second counting means for selecting a VCO frequency range among the plurality of VCO frequency ranges such that the VCO free-running frequency obtained through the selected range gives the closest value to the reference frequency. The state machine comprises means for decrementing the reference count value provided by the second counting means and also means for comparing the decrementation duration to the counting duration of the second counting means. The selection of the best VCO frequency range is based on this comparison.

Apparatus and method for setting VCO free-running frequency

A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; depositing a first layer of a conductive material to fill the first stud openings and define first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; depositing a thick insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; depositing a layer of polysilicon; patterning the polysilicon layer to define polysilicon lands containing the first contact studs at the desired locations; selectively implanting to define the source and drain regions of the PFET devices and interconnection conductors; depositing a cap layer; depositing a second thick passivating layer forming second stud openings in the second thick passivating layer to expose desired portions of the polysilicon lands and/or portions of the first contact studs; depositing a second layer of conductive material to define second contact studs; and planarizing the structure to make the top surface of the second contact studs coplanar with the surface of the second thick passivating layer.

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Mennecy, France

Vincent Vallet