Exar Corporation

Sierra Semiconductor

Vincent S Tso

Frank M Dunlap

James Ho

Roubik Gregorian

Christopher G Arcus

Mir Bahram Ghaderi

Timothy Lu

Shin Chung Chen

Manop Thamsirianunt

Johnny Lee

Bahram Ghaderi

James B Ho

Sunil Jaggia

A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a ground potential is varied. Optionally, the charge pump is disposed as part of a phase-locked loop (PLL), the input signals are produced by a phase/frequency detector, and current flow at the output node controls an oscillator element.

Low power charge pump

A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.

Interleaved pulse-extended phase detector

To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop's voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.

Detection of a closed loop voltage

A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the replication block receives first and second supply voltages and generates a second differential voltage. The source-follower stage of the output block receives the second differential voltage and generates a third differential voltage. The feedback control block receives the third differential voltage and generates a differential control voltage applied to the output block. The generated differential output voltage stays within predefined limits, such as those defined by the LvPECL standard.

CMOS LvPECL driver with output level control

Method and circuitry for selecting phases while avoiding glitches in the output signal during phase switching. An integrated circuit having a plurality of input terminals coupled to receive a respective plurality of clock signals having different phases, and a plurality of control terminals coupled to receive a respective plurality of phase selection signals. The circuit is configured to output a first selected clock signal from the plurality of clock signals in response to a first combination of the phase selection signals, and further configured to switch from the first selected clock signal to a second selected clock signal in response to a second combination of the phase selection signal. The circuit disengages the first clock signal after the second phases selection signal is engaged.

High speed phase selector

A duty cycle control circuit that consumes lower power and smaller silicon area, and is less susceptible to noise or jitter. In one embodiment, the invention includes a divide-by-two circuit that is edge triggered and generates a signal at its output with half the frequency of the input signal but with a 50% duty cycle. The divide-by-two circuit is followed by a frequency restore circuit that restores the original frequency of the input signal but with its duty cycle regulated at about 50%, or any other desired level.

Universal duty cycle adjustment circuit

The present invention is directed to providing a phase detector capable of establishing phase-locked-loop operation in a highly accurate and reliable manner. For example, exemplary embodiments detect a phase difference between at least two input signals to phase lock the input signals to one another. Exemplary embodiments include two phase detectors each of which receives the two input signals (e.g., three-state phase detectors), and each of which is forced to operate outside of its dead-band region by introducing predetermined phase delays for its inputs. Each of the two phase detectors detects a phase difference between its respective inputs. The two phase differences are then combined to produce a composite output signal formed as a net charge proportional to the net phase difference detected by the two phase detectors.

Three-state phase-detector/charge pump with no dead-band offering

A power supply self adjusted circuit that can sense a power supply voltage and detect whether the power supply is of a first value (e.g., 5V) or a second value (e.g., 3.3 V). In the case of a modem system, the power supply self adjusted circuit then adjusts the modem system accordingly. Hence, using this circuit, a modem or other signal processing circuit can be designed to work for both 5V and 3.3V power supply systems, for example. Futhermore, the power supply self adjusted circuit enables a modem system to automatically adjust itself when the power supply is switched from 5V to 3.3V or vice versa, without any manual intervention from the user. This capability is important for increasingly-popular PC Card- modems.

Power supply self-adjusted circuit for dual or multiple voltage

A pro-capture circuit for a phase locked loop detects when the phase locked loop is operating outside of its operating range, and then forces the phase locked loop back into the proper range. The principle of detection is general and may be adapted to work in distinct phase locked loop designs. More particularly, the pro-capture circuit is used in a phase locked loop having a normal operating range in which an output signal of the phase locked loop varies between a minimum normal value and a maximum normal value. The pro-capture circuit includes circuitry for sensing when the output signal is outside the normal operating range and circuitry for forcing the output signal to reenter the normal operating range. In accordance with another embodiment, a phase locked loop includes a voltage controlled oscillator that produces an output signal of a controlled frequency in response to a voltage input signal, circuitry for sensing when the output signal is outside a normal operating range by sensing when the voltage input signal is outside a corresponding normal operating range, and circuitry for forcing the output signal to a predetermined level within the normal operating range by forcing the voltage input signal to a corresponding predetermined level within the normal operating range.

Pro-capture circuit for phase locked loop circuits

A virtual sensing system includes a sensing network that is external to a standard cell for sensing a reference current in the standard cell and for generating a scaled current without breaking the reference current path and without inserting any sensing device in series with the reference current. The reference current can be used, for example, for duplication and/or scaling.

Growing community of inventors

Milpitas, CA, United States of America

Vincent S Tso