Arm Limited

Ampere S.a.s.

Vincent Rezard

Vladimir Vasekin

David Michael Bull

Cédric Denis Robert Airaud

Antony John Penton

Sébastien Aubert

Philippe Weingertner

Anton Antonov

Sebastien Aubert

An apparatus comprises associating circuitry to associate an indirect prefetch condition with a memory access request when hint information indicates that the data to be accessed in response to the memory access request is address indicating data which is to be used to generate a second address for a subsequent memory access request. A second address can be generated using the address indicating data, and a prefetch memory access request can be issued to seek to make data at the second address available in the associated cache.

Cache prefetching

Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.

Treating multiple cache lines as a merged cache line to store multiple blocks of data

Growing community of inventors

Vence, France

Vincent Rezard