Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Vincent Lorrain

Olivier Bichler

Antoine Dupret

Johannes Christian Thiele

Marc Duranton

Mickael Guibert

David Briand

An electronic calculator comprises a plurality of electronic calculation blocks, each of which is configured to implement one or more respective processing layers of an artificial neural network. The calculation blocks are of at least two different types among: a first type with fixed topology, fixed operation, and fixed parameters, a second type with fixed topology, fixed operation, and modifiable parameters, and a third type with modifiable topology, modifiable operation, and modifiable parameters. For each processing layer implemented by the respective calculation block, the topology is a connection topology for each artificial neuron, the operation is a type of processing to be performed for each artificial neuron, and the parameters include values determined via training of the neural network.

Electronic calculator for the implementation of an artificial neural network, with calculation blocks of several types

A computer-implemented method for coding a digital signal intended to be processed by a digital computing system includes the steps of: receiving a sample of the digital signal quantized on a number Nof bits, decomposing the sample into a plurality of binary words of parameterizable bit size N, coding the sample through a plurality of pairs of values, each pair comprising one of the binary words and an address corresponding to the position of the binary word in the sample, transmitting the pairs of values to an integration unit in order to carry out a MAC operation between the sample and a weighting coefficient.

Method and device for binary coding of signals in order to implement digital MAC operations with dynamic precision

A memory circuit for storing parsimonious data and intended to receive an input vector of size Iz, includes an encoder, a memory block comprising a first memory region and a second memory region divided into a number Iz of FIFO memories, each FIFO memory being associated with one component of the input vector, only non-zero data being saved in the FIFO memories, a decoder, the encoder being configured to generate an indicator of non-zero data for each component of the input vector, the memory circuit being configured to write the non-zero data of the input data vector to the respective FIFO memories and to write the indicator of non-zero data to the first memory region, the decoder being configured to read the outputs of the FIFO memories and the associated indicator in the first memory region.

Memory circuit for storing parsimonious data

A processor for computing at least one convolution layer of a convolutional neural network is provided, in response to an input event, the convolutional neural network comprising at least one convolution kernel, the convolution kernel containing weight coefficients. The processor comprises at least one convolution module configured to compute the one or more convolution layers, each convolution module comprising a set of elementary processing units for computing the internal value of the convolution-layer neurons that are triggered by the input event, each convolution module being configured to match the weight coefficients of the kernel with certain at least of the elementary processing units of the module in parallel, the number of elementary processing units being independent of the number of neurons of the convolution layer.

Device and method for calculating convolution in a convolutional neural network

A computer based on a spiking neural network, includes at least one maximum pooling layer. In response to an input spike received by a neuron of the maximum pooling layer, the device is configured so as to receive the address of the activated synapse. The device comprises an address comparator configured so as to compare the address of the activated synapse with a set of reference addresses. Each reference address is associated with a hardness value and with a pooling neuron. The device activates a neuron of the maximum pooling layer if the address of the activated synapse is equal to one of the reference addresses and the hardness value associated with this reference address has the highest value from among the hardness values associated with the other reference addresses of the set.

Computer for spiking neural network with maximum aggregation

A device for distributing the convolution coefficients of the least one convolutional kernel of a convolutional neural network is provided, the coefficients being carried by an input bus, to a set of processing units in a processor based on a convolutional-neural-network architecture. The device comprises at least one switching network that is controlled by at least one control unit, the switching network comprising a set of switches that are arranged to apply circular shifts to at least one portion of the input bus. For each convolution kernel, each control unit is configured to dynamically control certain at least of the switches of the switching networks in response to an input event applied to the convolution kernel and at least one parameter representing the maximum size of the convolution kernels.

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Palaiseau, France

Vincent Lorrain