Qualcomm Incorporated

Vincent Loncke

Thomas J Richardson

Joseph Binamira Soriaga

Shrinivas Kudekar

Gabi Sarkis

Jing Jiang

Yi Cao

Alexandros Manolakos

Krishna Kiran Mukkavilli

Renqiu Wang

Se Yong Park

Girish Varatkar

Junyi Li

Karl Georg Hampel

Ashwin Sampath

Yang Yang

Hari Sankar

Sundeep Rangan

Sathyadev Venkata Uppala

Joshua Lawrence Koslov

Siddharth Ray

Edward Knapp

Victor A Abramsky

Raghunath Kalavai

Mohamad M Mansour

Krishna G Murti

Mohammad M Mansour

Pramod K A Rao

Thomas Joseph Richardson

Thomas Richardson

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication relay may receive, via a first wireless link with a base station, a scheduling request that identifies scheduling information for scheduling transmission or reception of data via a second wireless link with a network node. The wireless communication relay may transmit, via the second wireless link, a scheduling command in accordance with the scheduling information. The wireless communication relay may transmit or receive, via the second wireless link, the data in accordance with the scheduling information. Numerous other aspects are provided.

Scheduling via wireless communication relay

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low density parity check (LDPC) codes. A method for wireless communications by wireless node is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes, puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes, and transmitting the punctured code word.

Puncturing for structured low density parity check (LDPC) codes

Certain aspects of the present disclosure relate to methods and apparatus for optimizing delivery of a transport block (TB) using code rate dependent segmentation.

Resource-based code block segmentation

Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.

Multiple low density parity check (LDPC) base graph design

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs. Accordingly, aspects of the present disclosure provide techniques for reducing delays in a processing pipeline by, in some cases, relaxing a dependency between updating bit log likelihood ratios (LLRs) and computing a posteriori LLRs.

Deeply-pipelined high-throughput LDPC decoder architecture

Various aspects described herein relate to techniques for rate matching and interleaving in wireless communications (e.g., 5G NR). In an example, a method described herein includes encoding one or more information bits to generate a first codeblock, rate matching the first codeblock to generate a second codeblock, segmenting, using bit distribution, the second codeblock into one or more sub-blocks each having a plurality of bits. The method further includes interleaving the plurality of bits on each of the one or more sub-blocks, concatenating, using bit collection, the one or more sub-blocks to generate a third codeblock in response to the interleaving, and transmitting a signal using the third codeblock.

Techniques for rate matching and interleaving in wireless communications

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to an efficient list decoder for list decoding low density parity check (LDPC) codes.

Efficient list decoding of LDPC codes

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In addition, the apparatus may bit reverse a binary sequence associated with each of the m consecutive elements. In an aspect, each of the m consecutive elements may include a different binary sequence. Further, the apparatus may determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. In addition, the apparatus may write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices.

Low latency bit-reversed polar codes

Certain aspects of the present disclosure generally relate to techniques for efficient, high-performance decoding of low-density parity check (LDPC) codes, for example, by using an adjusted minimum-sum (AdjMS) algorithm, which involves approximating an update function and determining magnitudes of outgoing log likelihood ratios (LLRs). Similar techniques may also be used for decoding turbo codes. Other aspects, embodiments, and features (such as encoding technique) are also claimed and described.

Adjusted min-sum decoder

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.

Early termination technique for LDPC decoder architecture

Encoders, decoders and methods of encoding and decoding data can comprise receiving source symbols in a first sequence, storing the source symbols to a first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence, determining if the memory contains all source symbols of a codeword, wherein the source symbols of a codeword are the symbols used to generate repair symbols for that codeword, generating repair symbols for the codeword, storing the repair symbols to a second memory in a third sequence, interlacing the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence, and outputting the stream of encoded symbols.

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Piscataway, NJ, United States of America

Vincent Loncke