Xilinx, Inc.

Other

Vincent L Tong

Shahin Toutounchi

Robert W Wells

Robert D Patrie

Zhi-min Ling

Jae Cho

Edwin W Resler

W Scott Bogden

Russell C Swanson

Sridhar Krishnamurthy

Jay T Young

Andrew W Lai

Randy J Simmons

Jeffrey V Lindholm

Teymour M Mansour

Roger D Carpenter

William R Troxel

F Erich Goettling

Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.

Methods of resource optimization in programmable logic devices to reduce test time

Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

Application-specific testing methods for programmable logic devices

A method in accordance with the present invention includes programming a plurality of semiconductor devices simultaneously, thereby dramatically increasing the number of devices programmed within a predetermined time. In one embodiment, this method includes arranging a first plurality of semiconductor devices into an array configuration. The first array is then programmed while a second plurality of semiconductor devices is arranged into the array configuration. The second array is then programmed, while the first array is unloaded and a third plurality of semiconductor devices is arranged into the array configuration. The present invention further includes the step of moving the first plurality of semiconductor devices in the array configuration to a programming position and the step of transferring the first plurality of semiconductor devices to an unloading position. The steps of moving or transferring includes providing a vacuum, mechanical pick-up, or magnetic pick-up for moving the semiconductor devices. In one embodiment, the step of loading is performed by a first arm capable of three dimensional movement, and the step of unloading is performed by a second arm capable of three dimensional movement independent of the first arm. In this embodiment, the step of moving or transferring is performed with a dual head array mechanism capable of moving independently from the first and second arms.

Device for programming multiple arrays of semiconductor devices

According to the present invention, means are provided for joining metal wire segments into one or more serpentine structures during the testing phase so that a signal applied at one end will be detected at the other end if the metal segments are continuous. Metal segments connected into one serpentine chain can be simultaneously tested for continuity from a single origin and destination. Preferably two serpentine chains are provided, physically interdigitated with each other so that electrical shorts between adjacent wire segments will cause a signal applied to one serpentine chain to be detected on the other serpentine chain.

Structure and method for testing wiring segments in an integrated

Device and method for programming multiple arrays of semiconductor

A dispenser for granular material or liquid includes a dispenser housing attached to a granular material/liquid-holding container. The housing has a hemispherical distal end including an exit port and a curved linear slot. A spherical casing having a common inlet/outlet port and an attached lever arm riding in the slot is positioned in the distal end of the housing so that in a fill position a measured quantity of the granular material/liquid passes from the container and fills a predetermined volume or two incremental volumes within the casing. Upon hand and finger movement of the lever arm to a first or second position the casing is sealingly rotated to a dispense position with cessation of access of material from the container and with the casing inlet/outlet port then aligned for at least partially aligned with the housing exit port. The measured volume or volumes then flow from the casing by gravity. The dispenser is held in an at least partial inverted position during the fill and dispense modes of operation. A leaf spring, which is cocked upon rotating motion of the lever arm and casing, positively returns the casing and lever arm to the fill position when the lever arm is released by the user after dispensing such measured quantity of the material.

Granular-liquid hand-held dispenser

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Fremont, CA, United States of America

Vincent L Tong