International Business Machines Corporation

Vincent L Rideout

Robert H Dennard

Donald A Soderman

Cheng-Yih Liu

Ronald P Esch

Robert M Folsom

George T Wenning

G Thomas Wenning

A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure. The electrical capacitance or storage node structure of each cell has increased electrical charge storage capacity and may be considered as a single capacitor. The single (storage) capacitor of each cell is provided between the source of the field effect transistor, a source of reference potential (reference plane) and the monolithic semiconductor substrate on which the memory is fabricated. The arrangement of the memory cells, the structure and material of each of the memory cells, and a method of fabricating the entire memory is disclosed. Also disclosed is an improved field effect transistor structure and process for fabricating same. The process of fabrication, cell arrangement and the improved storage node of each memory cell, as structurally fabricated and uniquely arranged, provides a monolithic memory having improved density and operating characteristics.

Method of fabricating random access memory device

One-device monolithic random access memory and method of fabricating same

In a one transistor, one capacitor N-channel polysilicon gate MOSFET RAM, having self-aligned contacts to silicon gates, an N-implant is used to both form bottom electrodes of the capacitors and to form depletion mode FET channels in peripheral circuits. Separate polysilicon layers are used for the gates of enhancement mode FETs and for the capacitor upper electrodes and depletion FET gates.

MOS RAM with implant forming peripheral depletion MOSFET channels and

A fabrication method is disclosed for providing self-aligned (i.e., misregistration tolerant or 'borderless') contact vias for electrical connections between metal interconnection lines and underlying doping semiconductive regions of an integrated circuit. The described method utilizes an oxidation barrier layer material which is patterned twice to provide, first, the recessed oxide isolation regions and, later, the self-aligned contact vias. An example of an n-channel FET embodiment is described wherein self-aligned contact vias are provided between aluminum interconnection lines and n-type doped source and drain regions. In the described method, at least a portion of the normally present misregistration region or border is eliminated between the boundary of a recessed isolation oxide and the boundary of the via. The latter is ultimately coincident with the boundary of an underlying doped region. Elimination of contact borders advantageously reduces the overall area required for the contact, and consequently, reduces the overall surface area of the integrated circuit chip. Additionally, the metal step coverage at the contact edges is improved over prior art etched contact vias. The self-aligned contact via is achieved by repeated patterning of an oxidation barrier coupled with the intermediate step of thermally growing a thick insulation oxide layer over areas wherein devices such as FET's or bipolar transistors will be formed.

Method of fabricating self-aligned contact vias

A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

Field effect transistors with polycrystalline silicon gate self-aligned

A process for providing ion-implanted regions in a substrate such as silicon beneath an existing layer such as silicon dioxide and being self-aligned to subsequently fabricated regions of said layer which includes providing a resist masking pattern above the existing layer wherein the resist masking pattern has vertical sidewalls (i.e., perpendicular to the upper surface of the substrate) or is undercut; ion-implanting impurities such as boron ions through the layer but not through the resist and portions of the layer beneath the resist; and depositing a layer of lift-off material such as aluminum on the existing layer and on the resist. The implantation step must be performed after providing the undercut resist masking pattern, but before depositing the layer of lift-off material in order to achieve the desired self-alignment feature. Because of the resist profile (i.e., vertical walls or being undercut) no lift-off material is deposited on the sidewalls of the resist and a gap is formed between the resist and that portion of the lift-off material which is above the existing layer. The resist pattern is removed along with the portion of the lift-off material layer deposited thereon. The now-exposed portion of the existing layer located beneath the previous resist pattern is then removed. Finally, the remaining regions of lift-off material are removed from above the regions of the existing layer. The ion-implanted regions occur in the substrate beneath the remaining portions of the existing layer, are self-aligned to the boundaries of said portions, and correspond to a negative image of the original undercut resist masking pattern.

Process for providing self-aligned doping regions by ion-implantation

A fabrication method for providing electrical isolation between transistors such as field effect transistors (FETs) which are fabricated on the same semiconductive substrate is described that uses a single doping step to form both the channel stopper field doping and the FET channel doping. An example of an n-channel FET embodiment is described wherein an extra p-type doping is provided in the field region which serves to prevent parasitic conductive channels from occurring under the thick field oxide. Such parasitic channels can undesirably cause electrical shorting between adjacent FETs of an integrated circuit. Extra p-type doping is also provided in the FET channel region and serves to raise the gate threshold voltage of the enhancement-mode FET to a level suitable for integrated circuit operation. In the described method a single implantation or diffusion doping step provides both the field and channel doping regions, thereby reducing the number of processing steps. This single doping step is facilitated by use of a thick field isolation oxide which is chemically vapor deposited at a relatively low processing temperature after performing the common doping step.

Method of fabrication for field effect transistors (FETs) having a

Enhancement-mode field-effect transistors (FETs) and depletion-mode FETs are provided on the same semiconductive substrate using five basic, lithographic, pattern-delineating steps. The five lithographic masking steps delineate in order:

Fabrication of integrated circuits containing enhancement-mode FETs and

Fabricating an integrated circuit array of FET one-device memory cells which includes providing a semiconductive substrate of a first conductive type; delineating field insulation regions; delineating polycrystalline silicon gate regions employing an oxidation barrier masking layer; introducing active impurities of a second and opposite conductive type into predetermined regions of the substrate to provide doped bit lines (FET drains), connection regions (FET sources), and lower conductive electrodes of the storage capacitors; next delineating upper polycrystalline silicon electrodes of the storage capacitors; growing silicon dioxide insulation over all portions of the structure except over the FET gate regions which are protected by the oxidation barrier masking layer; removing the oxidation barrier masking layer over the FET gates with an etchant; delineating contact holes to polycrystalline silicon capacitor electrodes and to FET sources and drains in circuits peripheral to the array of memory cells; and delineating the metallic-type high-conductivity electrical interconnection word line pattern. This fabrication procedure requires five basic lithographic (pattern delineating) masking steps. A high electrical conductivity word line is electrically connected to the gate of the FET by means of a 'self-registering' metallic line to polysilicon gate contact. This gate contacting technique is relatively more tolerant to misregistration between the FET gate lithographic pattern and the metallic interconnection line lithographic pattern than are previously known fabrication methods.

Method for fabricating FET one-device memory cells with two layers of

A method of fabricating a field effect transistor (FET) wherein a self-registered or misregistration tolerant electrical connection is provided between the gate electrode and a metallic interconnection line. The method involves a unique structure which includes a thick deposited oxide insulation layer and an etch stopping layer over doped silicon source and drain regions, over polysilicon gate electrode regions, and over field isolation regions. The etch stopping layer facilitates fabrication of a self-registering electrical connection between the gate electrode and a metallic interconnection line wherever desired. The thick deposited oxide layer provides reduced capacitive coupling between the insulated regions and the metallic interconnection line when compared to known self-registered gate contacting methods that employ only thermally grown oxide insulation. The method also includes the provision for controlling the removal of insulation over the gate electrode wherever desired without seriously degrading the insulation over other parts of the structure. The disclosed method further relates to fabricating an integrated circuit containing FETs having a self-registered electrical connection between the gate electrode and the metallic interconnection line, the gate electrode self-aligned with respect to the source and drain regions, and wherein FETs of the integrated circuit have: a channel region; a gate insulator; an electrically conductive gate electrode; source and drain regions; thick insulation over the source and drain and over the gate electrode except in the contact areas; field isolation or field shield regions between FETs of the integrated circuit; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line.

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Mohegan Lake, NY, United States of America

Vincent L Rideout