Hyundai Electronics America, Inc.

National Semiconductor Corporation

Rohm Gmbh

Vincent L Fong

Manzur Gill

A flash memory system and method for providing an array of erased flash memory cells having a reduced dispersion of erased threshold voltages. The cells of the system are erased in bulk, preferably utilizing some form of cold electron injection, and the cells are tested to determine whether the erased threshold voltage falls between a predetermined target maximum threshold voltage and a predetermined target minimum threshold voltage. In the event one or more cells has been over erased so that the measured threshold voltage is less than the target minimum values, all of the cells are lightly programmed so as to increase the actual threshold voltage. The light programming is repeated until all of the cells have an actual threshold voltage that exceeds the target minimum but is less than the target maximum.

Apparatus and method for reducing erased threshold voltage distribution

A flash memory system including an array of flash memory cells and at least one programmed reference cell and at least one erased reference cell disposed in a common integrated circuit. Memory array read operations are carried out by reading the two reference cells and the target cell of the memory array. The two reference cells produce a programmed reference output and an erased reference output which are averaged to provide a reference value to be compared with the read output of the target cell. In that the reference value is derived by on-chip programmed and erased cells, the reference value will automatically adapt to changes in the fabrication process, temperature, operating voltages and the like. Preferably, the reference cell outputs are also utilized to adaptively control the programming and erasing of the memory array cells so as to control the erased and programmed threshold voltages of the array cells.

Flash memory having adaptive sensing and method

A Low-voltage Electrically Erasable, Electrically Programmable Read Only Memory (EEPROM) and a method for reading memory cells in the EEPROM. During a read operation address input is provided to an address latch and edge detector, which supplies a changed address signal to a charge-sharing word line voltage generator, supplies word line address signals to a word line address decoder, and supplies bit line address signals to a bit line address decoder and sense amplifier circuit. The word line address decoder provides a positive voltage from a positive voltage source to a selected word line in the memory array and provides a voltage that is negative with respect to ground to deselected word lines. The bit line address decoder and sense amplifier circuit grounds selected source bit lines and senses drain to source current to read the memory cells. The charge-sharing word line voltage generator and charge-sharing bit line voltage generator use a plurality of charge pump circuits and capacitors to store and share charge with the word lines. The EEPROM has a reduced erased voltage threshold range by extending the erase time during erase operations.

Low-voltage EEPROM using charge-pumped word lines

A transition detection circuit is provided comprising input means receiving the signal to be monitored for generating a first pulse having a first predetermined pulsewidth when a transition occurs in the signal being monitored; and output means responsive to the first pulse from the input means for generating a second pulse having a second predetermined pulsewidth which is less than the first predetermined pulsewidth. The present invention permits a large number of signals to be monitored for transition yet provide a highly precise output pulsewidth, all with a minimum of circuitry. Preferably the input means include a plurality of input channels, each channel being assigned to a different signal being monitored and each channel providing the first predetermined pulsewidth using simple, non-precision time delay circuits. The output state employs a single, high precision time delay circuit to provide the second predetermined pulsewidth.

Transition detector circuit

A circuit for detecting the transition of the state of logic signals at a plurality of input terminals is provided. The circuit has a transition detecting block connected to each input terminal which generates a pulse at the transition of a logic signal at the input terminal, an OR logic block connected to each transition detecting block for generating a combined logic signal from the transition detecting blocks, and a latch having SET and RESET input nodes and an output node. The SET input node is connected to the OR logic block so that the output node switches into a first logic state from a second logic state responsive to the combined logic signal on the SET input node. The circuit also has a delay unit connected to the OR logic block and to the RESET input node of the latch which precisely delays the combined logic signal to the RESET input node so that the output node of the latch switches back to the second logic state. A pulse is thus generated at the output node responsive to logic signal transitions at the input terminals. The pulse has a width controlled by the delay unit.

Transition detection circuit

A sense amplifier which is tolerant under differences in layout orientation, power supply variations and process variations is presented. The sense amplifier, operates between first and second power supplies and has two MOS transistors, each of which has a drain effectively connected to its gate to operate as functional diodes, connected in series between the first and second power supplies. The input terminal of the amplifier is connected to a node in series between the two MOS transistors and an inverter has its input node connected to the series node. The inverter's output node is coupled to the output terminal of the sense amplifier. The inverter, being responsive to a voltage at the input node, is set into one of two logic states so that a current at the sense amplifier's input terminal determines a logic state at the output terminal.

High-speed current sense amplifier

An MOS oscillator circuit which is relatively immune to power variations in the supply is presented. A capacitor is charged and discharged in responsive to the feedback signal from a Schmitt trigger circuit. The current to charge and discharge the capacitor is generated by a current mirror which is regulated by a constant voltage generator for immunity from power supply variations.

Power supply compensated MOS Schmitt trigger oscillator

An output buffer circuit, which reduces its switching speed in response to the operation of a neighboring output buffer circuit, is presented. The output buffer circuit has a pair of drive transistors which switch complementarily in responsive to an input signal to the buffer circuit. In normal operation, each of the drive transistors is driven by a speed-up block for high-speed switching. When a similar drive transistor of a neighboring output buffer circuit is also switching, the speed-up block is switched off so that the drive transistor of the first output buffer circuit switches in a slower mode to avoid noise generation. The noise reduction connection between output buffer circuits is in the form of a daisy chain.

Output buffer circuit with noise reduction circuit

A memory array formed from single transistor flash cells employs prevention circuitry for minimizing the effect of any floating gates in an over-erased state when accessing data stored in the memory array device. The prevention circuit includes a column line coupling a current limiting device in each row together in a common column. The memory array device also employs a row current limiting device which couples that row of flash cells to the erase potential. The second row switching means is activated to prevent a false signal generated by an over-erased flash cell in the same column as a selected flash cell being accessed for data from masking the data retrieval from the desired flash cell.

One transistor cell flash memory assay with over-erase protection

The present invention provides protection against the effects of overerasure while essentially maintaining a single transistor per memory cell through the use of an additional transistor for each row of memory cells. The added transistor is a positive voltage threshold device which is coupled between the connected sources of the floating gate transistors and a read input line to limit the threshold voltage. For programming, a second transistor with a negative voltage threshold is coupled in the same manner, but is coupled to a program input line. The positive threshold transistor prevents an unselected transistor from turning on during a read operation.

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Fremont, CA, United States of America

Vincent L Fong