Advanced Micro Devices Corporation

Advance Micro Devices, Inc.

Advanced Micro Device, Inc.

Vincent K Win

Andrew K Chan

Cuong O Trinh

Behzad Nouban

Mark Kwan

An apparatus for controlling the power consumption of a programmable logic device which has a plurality of output signals comprising a programmable switch coupled to each one of the logic signal outputs of the programmable logic device. The programmable switch may include a sense amplifier coupled to each one of said logic signal outputs; a first transistor coupled between said amplifier and ground; a latch coupled to the gate of said first transistor; a second transistor responsive to a first control signal; and an electrically erasable programmable read only memory (EEPROM) cell, coupled to said latch and responsive to a second control signal, said second transistor and said EEPROM cell providing a state signal to said latch.

Programmable sense amplifier power reduction

A self-latching logic gate is disclosed which includes a first logic gate circuit for generating an output signal representative of a function of two or more input signals. The first logic gate circuit includes a first logic gate having at least two transistors, each transistor having first, second and third terminals. The first terminals of each transistor are connected to provide an output terminal for the self-latching logic gate and the first logic gate circuit. The second terminals of the transistors provide first and second data input terminals for the logic gate circuit. The third terminals of each transistor are connected to a common termination (i.e. ground). First and second complementary mode transistors are provided. Each includes first, second and third terminals, with the first terminal of the first transistor being connected to a source of electrical potential, the second terminals of the first and the second transistors being connected to each other to provide a common input terminal for the first and second transistors, the third terminal of the first transistor and the first terminal of the second transistor being connected to the output terminal of the first logic gate, and the third terminal of the second transistor being connected to ground. A second logic gate circuit is provided for including a second logic gate having first and second input terminals, the first input terminal being connected to the output terminal of the first logic gate circuit, the second input terminal providing a latch input terminal for the self-latching gate, and the output terminal of the second logic gate being connected to the common input terminal of the first and second transistors. In a specific embodiment, the present invention provides a NOR gate with a self-latching output, with minimal parts count and power consumption, which is suitable for use in a system. In further more specific embodiments, the invention includes circuitry for verifying the state of the array, circuitry for changing the polarity of the array output and circuitry for providing system security all with minimal parts counts and power consumption.

Self-latching logic gate for use in programmable logic array circuits

An improved address transition detector for use in PAL circuits is disclosed. The invention provides a predetermined logical output on a transition detection signal (TDS) bus for a transition of the input address on an input pad of the PAL. The TDS bus is used to trigger a phi generator which controls sense amplifiers and latch blocks on the such that the circuitry is maintained in a low power stand-by mode. The detector includes a first inverter for buffering the address input to provide a first signal, a second inverter for inverting the first signal to provide a second signal and a comparator for providing the predetermined logical level on the TDS bus for a period of time after the first signal and the second signal have changed states.

Address transition detector for programmable logic array

An adaptive reference voltage generation circuit. The invention generates a reference voltage for a sense amplifier to provide bias voltages for cells in a type programmable logic array. The circuit of the invention includes a reference cell having characteristics substantially similar to the cells of the array. A reference voltage supply circuit is included for providing a reference voltage in response to any changes in the characteristics of the reference cell. In accordance with the method of the invention, the reference cell is programmed and erased whenever the cells in the array are programmed and erased. Thus the characteristics of the reference cell change in accordance with changes in the characteristics of the cells of the array. As the reference voltage of the circuit of the present invention changes inversely with changes in the characteristics of the reference cell, the circuit of the invention effectively compensates for changes in the characteristics of the cells in the array due to program and erase cycling thereof.

Adaptive reference voltage generation circuit for PLA sense amplifiers

Polarity option control logic is disclosed which provides an optimized design for a macrocell of a programmable logic array with a minimal parts count. The invention is designed for use with a register of the macrocell having first and second input paths, the first input path including an inverter, and first and second switches in each path respectively. The polarity option control logic of the present invention includes a first logic circuit for receiving a clock input and a polarity input signal and controlling the activation of the first switch in response thereto and a second logic circuit for receiving the clock input and an inverted polarity input signal and controlling the activation of the second switch in response thereto. When the polarity input signal is in a first state, the first input path is enabled via the first switch in accordance with the clock signal and when the polarity input signal is in a second state, the second input path is enabled via the second switch in accordance with the clock signal. In a particular embodiment, a macrocell is provided including polarity option control logic, a bypass option, a high speed multiplexer and an advantageous preload circuit that minimizes parasitic capacitances at the register input. Thus, a macrocell constructed in accordance with the present teachings, can be configured in a register mode with set, reset and preload features or a logic mode with an optimized speed path for both modes of operation.

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Milpitas, CA, United States of America

Vincent K Win