International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Infineon Technologies Ag

Other

Vincent James McGahay

Thomas M Shaw

Anthony K Stamper

John Anthony Fitzsimmons

Daniel C Edelstein

Michael Wayne Lane

Timothy Joseph Dalton

Conal Eugene Murray

Edward Crandal Cooney, Iii

Stephen Edward Greco

Lawrence Alfred Clevenger

Ping-Chuan Wang

Matthew Earl Colburn

Satyanarayana Venkata Nitta

Hazara Singh Rathore

Joyce C Liu

Stephen McConnell Gates

Henry Atkinson Nye, Iii

Jeffrey P Gambino

Sampath Purushothaman

Elbert Emin Huang

Andrew Herbert Simon

Xiao Hu Liu

Yiheng Xu

Kamalesh K Srivastava

Terence Lawrence Kane

John Patrick Hummel

Lee Matthew Nicholson

Habib Hichri

Rebecca D Mih

Brett H Engel

Joyeeta Nag

Sujatha Sankaran

Ronald Gene Filippi, Jr

Sanjay C Mehta

Christos Dimitrios Dimitrakopoulos

Erdem Kaltalioglu

Jonathan R Fry

Paul Stephen McLaughlin

Jason Paul Gill

Melissa Alyson Smith

Andrew J Martin

Thomas H Ivers

Kevin Shawn Petrarca

Rasit Onur Topaloglu

Michael Jay Shapiro

Nicholas A Polomoff

Jawahar P Nayak

Robert F Cook

Taryn J Davis

Yun Yu Wang

Shom Ponoth

Son Van Nguyen

Soon-Cheon Seo

Ronald G Filippi

Tze-Chiang Chen

William Thomas Motsiff

Shahab Siddiqui

Robert Michael Geffken

Darryl D Restaino

Christy Sensenich Tyberg

Stephan Alan Cohen

Lynne Marie Gignac

Matthew S Angyal

Charles Robert Davis

David C Thomas

Bhupesh Chandra

Ronald R Uttecht

Andrew P Cowley

Jia Lee

Jeffrey R Marino

Theodorus E Standaert

Zhong-Xiang He

Douglas Duane Coolbaugh

Christopher Vincent Jahnes

Richard Stephan Wise

Sandra Guy Malhotra

Richard Paul Volant

Junjing Bao

Yun-Yu Wang

Chandrasekhar Narayan

Jeffrey Curtis Hedrick

Christopher Joseph Waskiewicz

Ebenezer E Eshun

Edward William Kiewra

Kaushik Chanda

James Gardner Ryan

Anil Kumar Chinthakindi

Hormazdyar M Dalal

James J Demarest

Ian D Melville

William Francis Landers

Kelly Malone

Kunal Vaed

Roy Charles Iggulden

Du Binh Nguyen

Birendra N Agarwala

Scott W Crowder

Ronald Dean Goldblatt

Ernest N Levine

Embodiments of the disclosure provide a method to form an air gap structure. An opening is formed in a first dielectric layer between adjacent conductors. A first dielectric layer is formed over the opening to fill a first portion of the opening. A remainder of the opening is free of the first dielectric layer. A second dielectric layer is formed on a top surface of the first dielectric layer, with a remainder of the opening unfilled. The second dielectric layer is devoid of wiring. The remainder of the opening below the second dielectric layer defines an air gap structure. A wiring layer is formed above the air gap structure.

Method to form air gap structure with dual dielectric layer

An artificially oriented piezoelectric films for integrated filters and methods of manufacture. The method includes: forming a piezoelectric film with effective crystalline orientations of a polar axis rotated 90 degrees from a natural orientation for planar deposited piezoelectric films; and forming electrodes on a planar surface of the piezoelectric film. The piezoelectric film has an effective crystalline orientation of the polar axis in a horizontal orientation, with respect to the electrodes, and an effective crystalline orientation of the polar axis in a vertical direction adjacent to an underlying substrate.

Manufacturing method for an artificially oriented piezoelectric film for integrated filters

A structure includes an air gap structure including: an opening in a first dielectric layer between adjacent conductors, and a non-conformal dielectric layer over the opening. In some cases, the non-conformal dielectric layer narrows an end portion of the opening of the air gap but may not seal the opening. In other cases, the non-conformal layer may seal the end portion of the opening and include a seam therein. The air gap structure may also include a conformal dielectric layer on the non-conformal dielectric layer. The conformal layer either seals the end portion of the opening or, if present, seals the seam. The structure may also include a wiring layer over the air gap structure.

Dual dielectric layer for closing seam in air gap structure

A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.

Seal ring structure of integrated circuit and method of forming same

A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

Time temperature monitoring system

The present disclosure relates to semiconductor structures and, more particularly, to artificially oriented piezoelectric films for integrated filters and methods of manufacture. The structure includes: a piezoelectric film with effective crystalline orientations of the polar axis rotated 90 degrees from a natural orientation for planar deposited films; and a conductor pattern formed on a surface of the piezoelectric film.

Artificially oriented piezoelectric film for integrated filters

The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.

Arc-resistant crackstop

A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

Multiple-depth trench interconnect technology at advanced semiconductor nodes

The present disclosure relates to semiconductor structures and, more particularly, to continuous crackstop structures and methods of manufacture. The structure includes a continuous crackstop having a wall which switches back (switchbacks) on itself multiple times to form an enclosure about an active area of a chip.

Crackstop structures

Approaches for detecting wear in integrated circuit chips are provided. An on-chip sensor system includes an integrated circuit chip including a plurality of sensor groups. Each respective one of the sensor groups is structured and arranged to detect a measure of wear corresponding to a respective one of a plurality of failure mechanisms.

Electrical circuit odometer sensor array

The present disclosure relates to semiconductor structures and, more particularly, to segmented guard-ring and chip edge seals and methods of manufacture. The structure includes: a guard ring structure formed in a low-k dielectric material; and an edge seal structure formed through the low-k dielectric material to at least a substrate underneath the low-k dielectric material.

Segmented guard-ring and chip edge seals

The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.

Corrosion resistant chip sidewall connection with crackstop and hermetic seal

Growing community of inventors

Poughkeepsie, NY, United States of America

Vincent James McGahay