Zenith Data Systems Corporation

Vincent J Messina

Richard D Ball

Todd R Witkowski

John T Filion

A computer system has a memory and has a processor coupled to the memory, the processor having an access control arrangement for delaying completion of a memory access until the occurrence of a control signal. A deterministic circuit coupled to the-processor and the memory has a register arrangement containing control information loaded by the processor, the deterministic circuit having a signal generation arrangement for generating the control signal. The signal generating arrangement includes a selective delay arrangement which can selectively delay generation of the control signal during an access to the memory by a time interval having a duration which is a function of the control information in the register arrangement.

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Pittsfield Township, MI, United States of America

Vincent J Messina