Gte Laboratories Incorporated

Vincent J Barry

Thomas W Fitzgerald

Paul O Haugsjaa

Craig A Armiento

Marvin J Tabasky

Margaret B Stern

Harry F Lockwood

Chirravuri Jagannath

Mark A Rothman

Edward John Bawolek

Jeremiah P McCarthy

Brenda A Boucher-Puputti

A method of passively aligning optical receiving elements such as fibers to the active elements of a light generating chip includes the steps of forming two front and one side pedestal structures on the surface of a substrate body, defining a vertical sidewall of the chip to form a mating channel having an edge at a predetermined distance from the first active element, mounting the chip epi-side down on the substrate surface, and positioned the fibers in fiber-receiving channels so that a center line of each fiber is aligned to a center line of a respective active element. When mounted, the front face of the chip is abutting the contact surfaces of the two front pedestals, and the defined sidewall of the mating channel is abutting the contact surface of the side pedestal. The passive alignment procedure is also effective in aligning a single fiber to a single active element.

Method and device for passive alignment of diode lasers and optical

A method of passively aligning optical receiving elements such as fibers to the active elements of a light generating chip includes the steps of forming two front and one side pedestal structures on the surface of a substrate body, defining a vertical sidewall of the chip to form a mating channel having an edge at a predetermined distance from the first active element, mounting the chip epi-side down on the substrate surface, and positioning the fibers in fiber-receiving channels to that a center line of each fiber is aligned to a center line of a respective active element. When mounted, the front face of the chip is abutting the contact surfaces of the two front pedestals, and the defined sidewall of the mating channel is abutting the contact surface of the side pedestal. The passive alignment procedure is also effective in aligning a single fiber to a single active element.

A process for enhanced formation of vias in multilevel conductive structures for integrated circuit devices. A semiconductor wafer, bearing a multilayered first level metalization characterized by a tungsten alloy top layer, is annealed in a suitable ambient so as to form a distinctly colored superficial film atop the first level metalization. The interlevel dielectric is then deposited and subsequently selectively dry etched until the film becomes discernible, the film itself serving as an etch stop so as to protect the top layer of the first level metalization. Exposed portions of the superficial film are then removed through a standard plasma etch step. Remaining areas of the film promote intimate binding between the first level metalization and the interlevel dielectric.

Via formation for multilayered metalization

Method of fabricating monolithic integrated circuit structure incorporating a full-wave diode bridge rectifier of four Schottky diodes. A body of silicon is produced by growing an epitaxial layer of N-type silicon on a P-type substrate. P-type imparting material is diffused into the layer to form isolating barriers delineating first and second N-type zones separated from each other by intervening P-type material and third and fourth N-type zones which are contiguous. A mixture of titanium and tungsten is deposited on portions of the zones and heated to form a mixed silicide. Schottky rectifying barriers are produced at the interfaces of the mixed silicide and N-type zones. Conductive members are formed; a first conductive member is connected to the N-type material of the first zone and the silicide of the third zone, a second conductive member is connected to the N-type material of the second zone and the silicide of the fourth zone, a third conductive member is connected in common to the silicide of the first and second zones, and a fourth conductive member is connected to the N-type material of the third and fourth zones. An AC voltage applied across the first and second conductive members produces a DC voltage across the third and fourth conductive members.

Method of fabricating a diode bridge rectifier in monolithic integrated

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Framingham, MA, United States of America

Vincent J Barry