Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Eems Asia Pte Ltd

Vincent Ho

Juan Boon Tan

Fan Zhang

Wenhe Lin

Bei Chao Zhang

Young Way Teh

Yong Kong Siew

Haifeng Sheng

Lap Chan

Jae Gon Lee

Lee Wee Teo

Yu Jau Chen

Bangun Indajang

Asri Yusof

Wai Kin Chim

Wee Kiong Choi

Vivian Ng

Cheng Lin Heng

The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Poly profile engineering to modulate spacer induced stress for device enhancement

A method for forming a package-on-package structure is disclosed. The method comprises the step of providing a first semiconductor package. The first semiconductor package has at least one encapsulation layer formed on at least one side of the first semiconductor package. The method also involves the step of securing the first semiconductor package to a surface. The surface is adapted for receiving the first semiconductor package. The method further involves the step of reducing the thickness of the at least one encapsulation layer to a predetermined thickness. The at least one encapsulation layer having a portion distal the surface removed. More specifically, the thickness of the at least one encapsulation layer is reduced for providing a predetermined clearance from a second semiconductor package attachable to the first semiconductor package. The clearance is the distance between the at least one encapsulation layer of the first semiconductor package and a side of the second semiconductor package opposing thereto.

Method for forming a package-on-package structure

A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with first and second regions with a first device layer. A second device layer including nanocrystals is also formed. A cover layer is provided over the second device layer. The cover layer is patterned to expose portions of the second device layer in the first and second regions. The exposed portions of the second device layer in the first and second regions are processed to form modified portions. The processing of the exposed portions at least reduces the nanocrystals to a diameter below a threshold diameter in the modified portions. The modified portions are removed.

Patterning nanocrystal layers

Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.

Process to manufacture nonvolatile MOS memory device

Growing community of inventors

Singapore, Singapore

Vincent Ho