Cadence Design Systems, Inc.

Vincent Gregory Reynolds

Georgia Penido Safe

Amit Kumar Sharma

Yael Kinderman

Manu Chopra

Amit Aggarwal

Mirlaine Aparecida Crepalde

Abhishek Raheja

Nili Segal

David Spatafore

Adriana Cassia Rossi De Almeida Braz

Yumi Monma

Fernanda Augusta Braga

Amit Dua

Felipe Althoff

Lucas Martins Chaves

Julio Alexandre Silva Rezende

Pedro Bruno Neri Silva

Mariana Ferreira Marques

Yan Yagudayev

Devices, methods, computer readable media, and other embodiments are described for automated formal analysis and verification of a circuit design. One embodiment involves accessing a circuit design and a set of default verification targets for the circuit design. A plurality of partitions for the circuit design are then automatically generated, and a first partition is analyzed to generate a first set of verification targets for the first partition based on the set of default verification targets and a set of partition and schedule values for the first partition. A first formal verification analysis is performed on the first partition, the first set of verification targets, and the set of partition and schedule values, and a formal verification output is generated based on the first formal verification analysis. Various embodiments can additionally involve stagnation analysis and additional automation to customize the analysis for each partition.

Partition-based circuit analysis and verification

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

System, method, and computer program product for determining suitability for formal verification

A method for combining verification data may include using a processor, obtaining verification data and a verification model from each of a plurality of verification engines relating to different verification methods, the verification data relating to a plurality of verification tests that were conducted on a design under test (DUT) using the plurality of verification engines; using a processor, merging the verification models obtained from the plurality of verification engines into a merged verification model; using a processor, calculating a combined verification metric grade for a plurality of verification entities in the merged verification model using verification metric grades for each of the plurality of verification entities calculated from the verification data obtained from the plurality of engines and applying a combined verification metric grade rule; and outputting the combined verification metric grade via an output device.

Method and system for verification using combined verification data

Methods for debugging a failure in a logic circuit design simulation by tracing a X-value are provided. In one aspect, a method includes detecting during a X-propagation logic circuit design simulation a failure at a register transfer level of a logic circuit comprising one or more logic blocks and tracing a X-value in a data path of the one or more logic blocks until the X-value is observed in a control path of the one or more logic blocks. The method also includes identifying a logic block comprising a control signal of the control path in which the X-value is observed, and identifying the logic block in which the X-value is observed as a root cause of the failure. Systems and machine-readable media are also provided.

Debugging failures in X-propagation logic circuit simulation

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Maidenhead, United Kingdom

Vincent Gregory Reynolds