Koninklijke Philips Corporation N.v.

Nxp B.v.

U.S. Philips Corporation

Vincent Fillatre

David Canard

Jean-Robert Tourret

Fateh M Singh

Abdelilah Faleh

Digital spur reduction in which spurs are kept outside selected channels of interest. An integrated radiofrequency transceiver circuit has digital and analogue components, the circuit includes a radiofrequency signal receiver having a local oscillator signal generator configured to provide a local oscillator signal at a frequency fand a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency ffor operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.

RF digital spur reduction

Digital spur reduction in which spurs are kept outside selected channels of interest, with illustrative embodiments relating to an integrated radiofrequency transceiver circuit having digital and analogue components, the circuit having a radiofrequency signal receiver with a local oscillator signal generator configured to provide a local oscillator signal at a frequency fand a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency ffor operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.

A frequency tunable arrangement (ICT) comprises a tunable oscillator circuit (TOC) that provides an oscillator signal (OS). A controllable frequency divider circuit (CDIV, DBT, DBT, DBT, MUX) provides a frequency-divided signal (MO) on the basis of the oscillator signal. The frequency-divided signal has a frequency that is equal to the frequency of the oscillator signal divided by a division factor. The controllable frequency divider circuit provides any division factor among a set of division factors (4, 5, 6, 7, 8) in which for any division factor a ratio between that division factor and a lower division factor closest thereto, if existing, does not exceed 1.25.

Frequency tunable arrangement

The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a phase/frequency comparator PD, which supplies a regulation signal Tun, which is subjected to pulse width modulation according to the difference observed. The device also includes a current source, which is designed to emit a charge current Ics, with a value which is controlled by the regulation signal Tun. The device further includes a capacitive element Cs, which is designed to generate the control signal Vcnt, under the effect of the charge current Ics. By means of a regulation signal Tun, which has a frequency which is virtually constant, the invention makes it possible to impose high-frequency variations on the control signal Vcnt.

Device for comparison of frequencies with low temporal inertia

The invention relates to a frequency converter FCV comprising a frequency divider FRACN, and an input port REG intended to receive a control word N(1:L) which determines a division ratio between the input FLO and output FDIV frequencies of the frequency divider FRACN. The frequency converter in accordance with the invention FCV additionally comprises interface means INT, arranged between the input port REG and the frequency divider FRACN, and intended to carry out a conversion of a control word value N(1:L) to a first and a second parameter M(1:L-P) and k(1:P) which jointly define a non-integer value of the division ratio of the frequency divider FRACN. The invention enables the user to program the frequency divider FRACN by means of a unique control word N(1:L), while customarily two control words are necessary to program non-integer division ratios.

Frequency converter enabling a non-integer division ratio to be programmed by means of a unique control word

Phase-locked loop enabling the generation of a reference signal having a high spectral purity

A frequency divider DIV/4 composed of memory cells (DL1 . . . DL4) realized in ECL technology, whose data paths constitute a loop, the data output Q4 of the last memory cell DL4 being cross-connected to the data input D1 of the first memory cell DL1. The clock inputs Ck of the memory cells DL1, DL3 of the odd rank are connected to the input IN of the frequency divider circuit DIV/4, while the others are cross-connected to said input. Such a frequency divider generates a noise having a unique frequency which is twice the frequency of the input signal, irrespective of the division ratio obtained.

Low-noise frequency divider

A controlled current source is disclosed which receives a control signal and supplies a current at an output. The current source includes a power module having a plurality of parallel-arranged power transistors, whose collectors are jointly connected to the output of the current source, a control module to receive the control signal, and an output to supply a signal enabling the power transistors to be turned on, wherein, the emitters of the power transistors are jointly connected to the output of the control module, the output for supplying a current whose value depends on the value of the control signal, the bases of the power transistors being permanently subjected to a voltage of a predetermined value enabling the power transistors to be rendered potentially conducting. By pre-charging the parasitic capacitances of the power transistors, the transistors are turned on at an accelerated rate.

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Thaon, France

Vincent Fillatre