Intel Corporation

Vincent E Hummel

Edward Thomas Grochowski

Tse-Yu Yeh

Achmed Rumi Zahir

Ralph Michael Kling

Hans J Mulder

Harsh Sharangpani

A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single stack. Return addresses are written into the stack and read out of the stack at an entry/exit register interior to the stack. The stack has a lower portion below the entry/exit register for maintaining both actual and speculative return addresses, and an upper portion above the entry/exit register for maintaining return addresses that have been speculatively popped out. A branch history register keeps an ongoing record of the most recent calls and returns. In the event of a pipeline flush, such as would be caused by a branch mispredict, the contents of the branch history register are examined to determine how to adjust the contents of the stack. One or more depth counters keep track of which contents in the branch history register are to be examined.

Bi-directional return register stack recovery from speculative execution of call/return upon branch misprediction

In one method, a predicted predicate value may be determined. A predicated instruction is then conditionally executed depending on the predicted predicate value. For example, in accordance with one embodiment of the present invention, a predicate table stores historical information corresponding to a predicate. A pipeline coupled to the table receives a predicted predicate value calculated from the historical information. The pipeline may use this predicted predicate value to conditionally execute a predicated instruction. The actual predicate value is provided back to the predicate table from the pipeline.

Predicate prediction based on a predicated predicate value

An embodiment of the invention is directed to a dynamic branch prediction method in which a first taken/not-taken prediction is provided responsive to an address using a saturating counter branch predictor. A second taken/not-taken prediction responsive to the address resulting in a hit in a local branch history table is provided. In addition, a hit/miss indication for the address is provided. The second prediction is selected for the address if the indication is a hit, and the first prediction is selected if the indication is a miss.

Branch predictor with saturating counter and local branch history table with algorithm for updating replacement and history fields of matching table entries

A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single stack. Return addresses are written into the stack and read out of the stack at an entry/exit register interior to the stack. The stack has a lower portion below the entry/exit register for maintaining both actual and speculative return addresses, and an upper portion above the entry/exit register for maintaining return. addresses that have been speculatively popped out. A branch history register keeps an ongoing record of the most recent calls and returns. In the event of a pipeline flush, such as would be caused by a branch mispredict, the contents of the branch history register are examined to determine how to adjust the contents of the stack. One or more depth counters keep track of which contents in the branch history register are to be examined.

Return register stack target predictor

Method and apparatus for predicting a predicate based on historical information and the least significant bits of operands to be compared

An apparatus and method for cycle accounting for a microprocessor are disclosed, in which a performance monitor includes a plurality of silos, a prioritizer, and a combiner. The silos receive delay reason signals from the main processor pipeline, and output staged signals. The prioritizer receives the staged signals, and outputs a plurality of prioritized signals. The combiner selectively combines various of the prioritize signals, and provides signals indicative of microprocessor performance. Each silo includes, in series, a plurality of stages, with each stage containing a single latch. The stages of the silo are synchronized with the stages of the main processor pipeline. The performance monitor operates in real-time, at the same frequency as the microprocessor, and in parallel to the main processor pipeline, and correctly accounts for buffering effects of decoupling buffers. Outputted signals include various signals indicative of microprocessor performance, for example, cache misses, branch mispredictions, and so forth, but only for those miss-events that contribute to a program's visible delay, thereby providing an accurate picture of where cycles are being wasted.

Apparatus and method for cycle accounting in microprocessors

An apparatus and method for cycle accounting for a microprocessor are disclosed, in which a performance monitor includes a plurality of silos, a prioritizer, and a combiner. The silos receive delay reason signals from the main processor pipeline, and output staged signals. The prioritizer receives the staged signals, and outputs a plurality of prioritized signals. The combiner selectively combines various of the prioritize signals, and provides signals indicative of microprocessor performance. Each silo includes, in series, a plurality of stages, with each stage containing a single latch. The stages of the silo are synchronized with the stages of the main processor pipeline. The performance monitor operates in real-time, at the same frequency as the microprocessor, and in parallel to the main processor pipeline. Outputted signals include various signals indicative of microprocessor performance, for example, cache misses, branch mispredictions, and so forth, but only for those miss-events that contribute to a program's visible delay, thereby providing an accurate picture of where cycles are being wasted.

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Cambridge, MA, United States of America

Vincent E Hummel