Interuniversitair Microelektronica Centrum (imec)

Other

Ami Semiconductor, Inc.

Semiconductor Components Industries, LLC

Imec

Vincent De Heyn

Guido V Groeseneken

Steven Thijs

Koen Reynders

Natarajan Mahadeva Iyer

Vesselin K Vassilev

Mahmud Zubeidat

Tom Daenen

Geert Gallopyn

Louis Vacaresse

Hugo Van Hove

Guido Groeseneken

An electrostatic discharge (ESD) protection circuit for the protection of an electronic circuit from an ESD event. The electronic circuit, in operation, is provided with a supply voltage and a reference voltage (typically electrical ground) via voltage terminals and/or power supply buses. The protection circuit includes two bipolar transistors in series, where the transistors are coupled between the supply voltage terminal/bus and the reference voltage terminal/bus. The bases of the transistors are coupled via a connection including two resistors in series, where the connection point between the two resistors is coupled with the connection point between the two transistors.

Electrostatic discharge protection circuit

A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline. The method may use a rectangular pulse testing set-up, also known as transmission line measurement set-up, with a single loadline characteristic to determine a portion or the complete ESD characteristic of the device-under test.

Method of determining current-voltage characteristics of a device

Electrostatic discharge protection device comprising a first highly p-doped region with a base contact, a first highly n-doped region with a collector contact, a second highly n-doped region with an emitter contact and located between the first highly p-doped region and the second highly n-doped region, the first highly p-doped region and the second highly n-doped region being applied in a weakly p-doped region which a has a lateral overlap extending towards the first highly n-doped region, the lateral overlap having a width, the first highly n-doped region being applied in a weakly n-doped region, the weakly p-doped region and the weakly n-doped region being applied in a more weakly n-doped region, and a highly n-doped buried layer located underneath the more weakly n-doped region and extending below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region. The device enables a lateral current component from the first highly n-doped region in the direction of the second highly n-doped region and a vertical current component from the first highly n-doped region via the buried layer in the direction of the second highly n-doped region. The width of the lateral overlap of the weakly p-doped region is determined in function of the predetermined ratio between the lateral current component and the vertical current component.

Layout configurable electrostatic discharge device for integrated circuits

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Braives, Belgium

Vincent De Heyn