Ati Technologies Ulc

Advanced Micro Devices Corporation

Vincent Cueva

Philip Ng

Vydhyanathan Kalyanasundharam

Benjamin Tsien

Anthony Asaro

Jimshed B Mirza

Greggory D Donley

Bryan P Broussard

Maggie Chan

Gia Tung Phan

Yaniv Adiri

Greggory Douglas Donley

A computing device and method controls power consumption of a graphics processing unit in the computing device by the GPU determining an allocated power for the USB device connected through a USB port, such as a USB-C port. The GPU issues allocated power information for the external USB device to cause the allocated power to be provided to the USB device and includes issuing allocated power information to a power delivery (PD) controller that is connected to a USB port. In some implementations, the GPU shifts at least a portion of the allocated power from the USB device back to the GPU in response to a usage change event associated with the USB device for improving GPU performance. The usage change event can be a disconnect event of the USB device, a power renegotiation event between the USB device and the GPU, or any other suitable usage change event.

Apparatus and method for providing subsystem processor based power shifting for peripheral devices

Apparatus and method for providing graphics processing unit (GPU) based power shifting for USB devices

A system including a gasket communicatively coupled between a unified northbridge (UNB) having a cache coherent interconnect (CCI) interface and a processor having an Advanced eXtensible Interface (AXI) coherency extension (ACE). The gasket is configured to translate requests from the processor that include ACE commands into equivalent CCI commands, wherein each request from the processor maps onto a specific CCI request type. The gasket is further configured to translate ACE tags into CCI tags. The gasket is further configured to translate CCI encoded probes from a system resource interface (SRI) into equivalent ACE snoop transactions. The gasket is further configured to translate the memory map to inter-operate with a UNB/coherent HyperTransport (cHT) environment. The gasket is further configured to receive a barrier transaction that is used to provide ordering for transactions.

Input/output memory map unit and northbridge

The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

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Markham, Canada

Vincent Cueva