Texas Instruments Corporation

Nxp B.v.

Vincent Chalendard

Gregory R Conti

Tom Waayers

Paul-Henri Pugliesi-Conti

Johan Corneel Meirlevede

Pascal Cussonneau

Michael Rodat

Benoit Drevet

Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

Testing of asynchronous reset logic

A system comprising processing logic adapted to determine a type of boot performed by the system and a storage coupled to the processing logic. The processing logic is configured to erase or invalidate a predetermined portion of the storage, and to activate or deactivate an interface by which the system is accessed, if the type of boot comprises a functional boot.

Security measures for preventing attacks that use test mechanisms

Growing community of inventors

Antibes, France

Vincent Chalendard