Northrop Grumman Systems Corporation

Trw Limited

Vincent C Moretti

Mark Kintis

Gregory S Caso

Donald R Martin

Andrew Donovan Smith

William Marvin Skones

Shimen K Claxton

Craig R Talbott

Dominic P Carrozza

Bert K Oyama

David A Wright

Barry Ross Allen

Ronald P Smith

David Joseph Brunone

Eric L Upton

Stuart T Linsky

Reginald Jue

Sam H Liu

Edward L Niu

Donald R Sentz

The invention is a receiver and a method of receiving data having a preferred application in a satellite receiver in accordance with the invention includes a memory () including an addressable storage array which stores a sequence of data samples contained in a time division multiplexed signal from a plurality channels (X, Y and Z) and outputs the stored data samples in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; and a decoder (), responsive to the data groups, which decodes the data samples within the data groups and outputs decoded data samples.

Buffering and sequencing of soft decisions of multiple channels into a single shared biorthogonal decoder

A receiver ( ) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver ( ) includes a specialized LNA ( ), frequency down-converter ( ) and ADC ( ) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter ( ) employs a suitable mixer ( ), BPA ( ), attenuator ( ), and transformer ( ) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC ( ). A specialized digital channelizer ( ) is included in the receiver ( ) that receives the digital signal from the ADC ( ), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC ( ) employs delta-sigma processing to provide digital conversion over the complete frequency band. In an alternate embodiment, the frequency down-conversion is performed in a double down-conversion process so that a less complex ADC ( ) can be used.

Wireless telecommunications multi-carrier receiver architecture

Receiver including frequency down-converter and analog-to-digital converter for a wireless telecommunication system

A receiver ( ) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver ( ) includes a specialized LNA ( ), frequency down-converter ( ) and ADC ( ) to perform the wideband signal processing while maintaining receiver performance. A specialized digital channelizer ( ) is included in the receiver ( ) that receives the digital signal from the ADC ( ), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC ( ) employs delta-sigma processing to provide digital conversion over the complete frequency band.

Multi-carrier receiver including an analog-to-digital converter for a wireless telecommunication system

Architecture for multi-carrier receiver

Receiver including low noise amplifier and frequency down-converter for a wireless telecommunication system

An initial entry processor ( ) for use in a processing satellite ( ) in a satellite based communications system ( ) is provided having a buffer ( ), a detection and timing circuit ( ) and an identity circuit ( ). The buffer ( ) stores an initial entry burst ( ) transmitted from at least one terrestrial terminal ( ) to the processing satellite ( ). The detection and timing circuit ( ) detects the initial entry burst ( ) and determines a time of arrival of the initial entry burst ( ) relative to an initial entry burst slot ( ). The identity circuit ( ) determines an identity of the terrestrial terminal ( ) that transmitted the initial entry burst ( ) such that the time of arrival is used by the identified terrestrial terminal ( ) during subsequent communications with the processing satellite ( ).

Onboard initial entry processor for facilitating a satellite communication

A power control system for a multi-carrier base station transmitter is capable of controlling power levels of individual RF carriers. The power control system has a multi-channel amplification system for converting a plurality of analog input signals into a plurality of amplified carrier signals. The amplification system also generates a plurality of reference signals corresponding to the amplified carrier signals. Furthermore, the amplification system generates a multi-carrier signal, where the multi-carrier signal includes a summation of the amplified carrier signals. A correlating power detection system is connected to the amplification system, where the correlating power detection system generates total power control signals based on the reference signals and the multi-carrier signal. The power control system also has an adjustment module connected to the amplification system and the power detection system, where the adjustment module controls amplification of the carrier signals based on the total power control signals. Sampling the amplified signals to obtain reference signals, and using these reference signals for control purposes allows greater power control than available under conventional approaches.

Analog power control system for a multi-carrier transmitter

Multi-carrier receiver for a wireless telecommunication system

A power control system for a multi-carrier base station transmitter is capable of controlling power levels of individual RF carriers. The power control system has a multi-channel conversion system for generating a plurality of analog reference signals corresponding to a plurality of digital input signals. The multi-channel conversion system also generates an analog multi-carrier signal and samples the multi-carrier signal. The multi-carrier signal represents a summed amplification of the digital input signals. A correlating power detection system is connected to the multi-channel conversion system and generates digital total power control signals based on the analog reference signals and the analog sampled multi-carrier signal. A feedback conversion module is connected to the multi-channel conversion system and the correlating power detection system and individually controls amplification of the digital input signals based on the total power control signals.

Digital power control system for a multi-carrier transmitter

An uplink demodulator system ( ) for use in a processing satellite ( ) in a satellite based communications system ( ) is provided with a first multiplexer ( ), a second multiplexer ( ), a multichannel preamble processor ( ), and a multichannel phase tracker ( ). The first multiplexer ( ) is operable to receive channelized data from a plurality of channelization modes at a plurality of inputs and operable to route the channelized data to a first output. The multichannel preamble processor ( ) is operable to determine a phase estimate for each channel of the channelized data. The multichannel phase tracker ( ) is operable to receive the phase estimates from the multichannel preamble processor ( ) and operable to track a phase for each channel of said channelized data to phase align each channel of said channelized data to corresponding uplink signals. The second multiplexer ( ) is operable to multiplex and route heavy encoded channelized data and light encoded channelized data to a second output where the multiplex channelized data is phase aligned with the corresponding uplink signals.

Uplink demodulator scheme for a processing satellite

A synchronization burst processor ( ) used in a processing satellite ( ) in a satellite based communications system ( ) is provided with a sync burst memory ( ), a first double correlator ( ), a second double correlator ( ) and a modulus module ( ). The sync burst memory ( ) stores at least one sync burst ( ) transmitted from a terrestrial terminal ( ) to the processing satellite ( ) where the sync burst ( ) is formed from a quadrature pair sample set &lcub;p, q&rcub;. The first double correlator ( ) performs an early correlation and a late correlation of the p samples relative to a sync burst slot ( ) to generate an early correlation Pe and a late correlation Pl. The second double correlator ( ) performs an early correlation and a late correlation of the q samples relative to the sync burst slot ( ) to generate an early correlation Qe and a late correlation Ql. The modulus module ( ) determines an early modulus Re and a late modulus Rl from the early correlations Pe and Qe and from the late correlations Pl and Ql. The early modulus Re and the late modulus Rl are used to determine if the sync burst ( ) is present in the sync burst slot ( ) and if the sync burst ( ) is early or late relative to the sync burst slot ( ).

Synchronization burst processor for a processing satellite

The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter ( ); a demultiplexer ( ), coupled to the analog to digital converter, a window presum ( ) having N outputs, coupled to the parallel data streams, each output being a function of a window presum function and data words from a plurality of the parallel data streams; and a cyclic shift ( &prime;), coupled to I output groups of data words.

Efficient digital channelizer system and method of operation thereof

The invention is an apparatus and process for performing a discrete Fourier transform and a digital channelizer which divides an input bandwidth into at least some of N channels. An apparatus for performing a discrete Fourier transform in accordance with the invention includes at least one discrete Fourier transform computation stage ( ), the at least one discrete Fourier transform computation stage having N inputs representing preselected frequency bands with each input containing an input signal containing real data and P actual outputs each containing an output signal, P being less than N, at least one of the P actual output signals containing a conjugate of one of the N input frequency bands; and a processing device ( ), coupled to at least one P actual output containing a signal which is a conjugate, which processes the conjugate as representative of one of the N input frequency bands.

Digital channelizer having efficient architecture for discrete fourier transformation and operation thereof

The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes a window presum ( ); a cyclic shift ( &prime;), coupled to the I output groups of date words, having I cyclic shift paths, each cyclic shift path being responsive to a different output group of data words to produce I output groups of data words, each cyclic shift path comprising a plurality of word shifting elements each responsive to a group of data words; and a discrete Fourier transform ( &prime;) coupled to the I output groups of cyclically shifted data words outputted from the cyclic shift.

Growing community of inventors

Torrance, CA, United States of America

Vincent C Moretti