Stmicroelectronics S.a.

Koninklijke Philips Corporation N.V.

Nxp B.v.

Stmicroelectronics (crolles 2) Sas

Other

Vincent Arnal

Joaquin Torres

Laurent Gosset

Joaquim Torres

Alexis Farcy

Sonarith Chhun

Michel Marty

Philippe Delpech

Laurent-Georges Gosset

Arnoud Willem Fortuin

Wim Besling

Sandra Lis

Arnoud Fortuin

A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:&#x2014;providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;&#x2014;depositing a metal layer on the exposed surface of conductive element;&#x2014;inducing diffusion of metal from the metal layer into a top section of the conductive element;&#x2014;removing the remaining metal layer;&#x2014;letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.

Fabrication of a diffusion barrier cap on copper containing conductive elements

A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.

Method for forming metal interconnects in a dielectric material

The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.

Formation of a reliable diffusion-barrier cap on a Cu-containing interconnect element having grains with different crystal orientations

The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fluidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of electrical interconnect segments and at desired lateral positions of fluidic-cooling channel segments. A metal filling is deposited in the recesses of the dielectric layer sequence so as to form the electrical interconnect segments and to form a sacrificial filling in the fluidic-cooling channel segments. Afterwards, the sacrificial metal filling is selectively removed from the fluidic-cooling channel segments.

On-chip interconnect-stack cooling using sacrificial interconnect segments

A process for fabricating an integrated electronic circuit comprises the formation of at least one air gap between interconnect elements above only a defined portion of a surface of a substrate, within an interconnect layer. The interconnect layer comprises a sacrificial material and extends beneath an intermediate layer of permeable material. The air gap is formed by removal, through the intermediate layer, of at least part of the sacrificial material by bringing the permeable material into contact with an agent for removing the sacrificial material, to which agent the permeable material is resistant.

Process for fabricating an integrated electronic circuit that incorporates air gaps

Deep isolation trenches having sides and a bottom are formed in a semiconductor substrate. The sides and the bottom are coated with an electrically insulating material that delimits an empty cavity, and forms a plug to close the cavity. The sides of the trench are configured with a neck that determines the depth of the plug, and a first portion that tapers outwards from the neck as the distance from the bottom increases. Deep isolation trenches may be applied, in particular, to bipole and BiCMOS circuits.

Deep insulating trench

A method for forming at least one conductive line intended to receive high-frequency or high-value currents, formed above a given portion of a solid substrate outside of which are formed other elements, including the steps of digging at least one trench in the solid substrate; forming an insulating area in the trench; and forming said conductive line above the insulating area.

High-frequency line

A method for forming a capacitor with metal armatures in metallization levels above an integrated circuit, including the steps of: depositing over the surface of an integrated circuit an insulating layer having a thickness ranging between 0.5 and 1.5 &mgr;m; digging into the insulating layer to form trenches, of which at least a portion in top view is parallel and separate from one trench to the other; depositing and leveling a metallic material to form conductive lines in the trenches; locally removing the insulating layer to remove it at least from all the intervals separating two conductive lines; conformally depositing a dielectric; and depositing and etching a second metallic material to at least completely fill the intervals between lines.

Manufacturing of capacitors with metal armatures

An inductance formed in an integrated circuit chip, formed of a plurality of parallel conductive lines, of optimized width, each conductive line being formed in the thickness of at least one insulating layer, these lines being interconnected by at least one perpendicular conductive segment.

High-frequency integrated inductive winding

An integrated circuit capacitor includes a substrate, a first metal electrode on the substrate, and a dielectric layer on the first metal electrode. The dielectric layer includes a homogeneous combination of at least two dielectric materials having permittivities varying in an opposite way based upon an electric field, with a proportion of each dielectric material being chosen so that the integrated circuit capacitor has a desired voltage linearity. A second metal electrode is on the dielectric layer.

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Grenoble, France

Vincent Arnal