International Business Machines Corporation

Vincent A Scotto

Frederick Buckley, Iii

Gerald Aberdeen Miller

Leland D Howe, Jr

Albert E Paniccia

Gerald A Miller

Clock generating apparatus for a computer system has selective pulse delay and pulse width control. Selection of pulse delay and pulse width is accomplished by loading registers with predetermined data patterns. The registers can be loaded under program control or by data entry units, such as a keyboard, switches, etc. The registers are located in coarse and fine pulse delay and pulse width adjustment units. These units have the same physical structure, but are functionally definable by a settable control element. A dither delay element is included in these coarse and fine adjustment units, and it is selectable to provide a small increment of delay. The coarse pulse delay and pulse width adjustment units also include pulse mode control circuitry to control operation in either normal oscillator mode or in single cycle mode.

Clock pulse generator with selective pulse delay and pulse width control

A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor as the shunt feedback and a second embodiment of the invention, to which this application is directed to, uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.

MOS interchip receiver differential amplifiers employing CMOS amplifiers

A negative shunt feedback amplifier is disclosed for connection to the output node of a complex complementary metal oxide semiconductor logic circuit to increase the performance and reduce the FET device size. A CMOS inverter is coupled to the amplifier to restore the logic levels and to form the logic output. A first embodiment of the invention uses a resistor feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the feedback impedance. The circuit has application in environments where a logic function requires a large number of FET devices resulting in a large output node capacitance and, thereby slowing the logic speed, as for example in a large DOT-OR circuit or at each output of a FET memory array.

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Endicott, NY, United States of America

Vincent A Scotto