Xilinx, Inc.

Coupang, Corporation

Vinay Verma

Sandor S Kalman

Jason Helge Anderson

Sanjeev Kwatra

Taneem Ahmed

Anirban Rahut

Gitu Jain

Xinli Bao

Satyavaraprasad Vadlamudi

Sudip K Nag

Christopher H Kingsley

Satyaki Das

Rajeev Jayaraman

Tiziano Cembali

Jing Li

Hasan Arslan

Hyun Jung Cho

Hui Xu

Michael Rowan Savio

Jitu Jain

Systems and methods of generating, for display on a graphical user interface (GUI), a personalized advertisement. The systems and methods can include receiving data indicative of initiating a browsing session, aggregating user activity data associated with a user of the application, the user activity data including current session data and/or past session data, applying machine learning on the user activity data to generate one or more excluded products, applying the one or more excluded products to a product database to generate a list of relevant products, ranking, using one or more ranking rules, the list of relevant products to generate a ranked list of relevant products, and sending, to the mobile device, the personalized advertisement including one or more relevant products from the ranked list of relevant products.

Systems and methods for generating a personalized advertisement

A system for generating adaptive notifications including processors and memories storing instructions that configure the processors to perform operations. The operations may include generating an item list for notifications to a client ID, selecting a first item from the item list for notification, the first item being selected having a highest priority score and a lowest lifecycle timer, encoding a first landing page by encoding a product code and a tracking cookie in a URL configured for redirection to a first webpage by a redirect server, and transmitting a first notification with a payload including the first landing page and a first message. The operations may also include after transmitting the first notification, modifying priority scores and updating lifecycle timers based on determining whether the client device visited the first landing page. Further, the operations may also include selecting a second item from the item list for notification.

Systems and methods for recurrent and adaptive electronic notifications

Within a system comprising a plurality of processors and a memory, a method of determining routing information for a circuit design for implementation within a programmable integrated circuit can include determining that nets of the circuit design comprise overlap and unrouting nets comprising overlap. A congestion picture can be determined that comprises costs of routing resources for the integrated circuit wherein the cost of a routing resource comprises a measure of historical congestion and a measure of current congestion, and wherein unrouted nets do not contribute to the measures of current congestion in the congestion picture. The method further can include concurrently routing a plurality of the unrouted nets via the plurality of processors executing in parallel according to the congestion picture and storing routing information for nets of the circuit design in the memory.

Multi-threaded deterministic router

A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.

In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.

Parallel process optimized signal routing

A method is provided for routing a circuit design netlist. Nets of the netlist are grouped into a plurality of sub-netlists. For each sub-netlist, nets of the sub-netlist are routed as a function of congestion between nets of the sub-netlist. Congestion between nets of other sub-netlists in the plurality of sub-netlists is not taken into account. If two or more nets of the netlist are routed through the same routing resource, a global congestion history data set is updated to describe congestion between all nets in the netlist, and the two or more nets of the netlist are unrouted. The two or more nets are each rerouted as a function of the global congestion history data set and congestion between nets of the same sub-netlist as the net.

Parallel signal routing

In one embodiment of the invention, a processor-implemented method is provided for routing of a partially routed circuit design. Modified signals of the partially routed circuit design are determined. A first set of routing constraints are applied by the processor to the unmodified signals of the circuit design. For each logic block of the circuit design, the number of the modified signals and the number of the unmodified signals connected to the logic block are determined. In response to one of the logic blocks having a ratio of the number of modified signals to the number of unmodified signals greater than a threshold ratio, the routing constraints are removed by the processor from one or more of the unmodified signals of the one of the logic blocks. The partially routed circuit design is then routed by the processor according to the remaining routing constraints, and the resulting netlist is stored.

Incremental placement and routing

Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.

Patterns for routing nets in a programmable logic device

Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Method and apparatus for facilitating signal routing within a programmable logic device

A method for completing the routing of a partially routed design is provided. The unrouted pins are routed to generate a first plurality of nets that may contain shorts or overlaps between the nets. The nets are analyzed to obtain timing information, and then divided into a set of critical and a set of non-critical nets. The non-critical nets are hidden, and the critical nets are rerouted to remove overlaps. The non-critical nets are then unhidden. The non-critical nets and rerouted critical nets are then rerouted so as to remove overlaps.

Incremental routing in integrated circuit design

A method for post-layout timing optimization is disclosed. The method performs timing analysis on a design to obtain timing information such as critical paths and slack values. Incremental placement based on the timing information is performed. A new routed design is generated by applying incremental routing to the result of incremental placement. The routed design is stored if its performance is better than the previous routed design. The above steps are repeated until a predetermined criterion is met.

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Fremont, CA, United States of America

Vinay Verma