The Penn State Research Foundation

Vinay Saripalli

Suman Datta

Vijaykrishnan Narayanan

Saurabh Mookherjea

Dheeraj Mohata

A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.

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University Park, PA, United States of America

Vinay Saripalli