Applied Micro Circuits Corporation

Edgeq, Inc.

Infinera Corporation

Vinay Ravuri

Sriram K Rajagopal

Keyur Chudgar

Biao Lu

How Tung Lim

Hariprasad Gangadharan

Loc Nhin Ho

Umesh Dattatraya Nimbhorkar

Chaekwan Lee

Mathivanan Prabhakaran

Prodyut Hazarika

Kamran Farshchi

Subhash Chandra Roy

Paramesh Gopi

Sharfuddin Syed

Satish Sathe

Gopalakrishnan Perur Krishnan

Kumar Sankaran

Yatindra Chugh

Vishwanatha Tarikere Basavaraja

Dmitriy Shtalenkov

Parameswaran Gopi

Tushar Tyagi

Tae Ryun Chang

Dimitry Vaysburg

System and method embodiments are disclosed for merging computing hardware datapath to reduce energy consumption and improve throughput of modem signal processing functions on a Modem. Compute-in-memory (CIM) is used for data access and processing in parallel using processing elements integrated within memory chip. The processing throughput may significantly improve since data is accessed directly from the computational memory storage in parallel for processing and the clock speed for data processing may run at a higher spec than conventional approaches. Energy consumption for Modem processing is also reduced.

Wireless baseband modem datapath using compute in memory

With advanced compute capabilities and growing convergence of wireless standards, there is requirement to run multiple wireless standards, e.g., 4G, 5G, and Wi-Fi, on a single hardware together. Typical solution includes reserving some computing resources for specific wireless standards. Such a resource strategy may not be optimized or efficient according to the real needs for various wireless standards. The present disclosure presents embodiments of using a unified resource controller to take multiple scheduling inputs across various wireless standards, allocate resources among a plurality of configurable processing units, and manage hardware components for data path accelerations including forward error correction, and signal processing implementation. The multiplexing multiple wireless technologies based on spectral utilization may improve the efficiency in power consumption and hardware resources utilization.

Systems and methods for multiplexing multiple wireless technologies in resource constrained environment based on spectral utilization

Advances in wireless technologies have resulted in the ability of a 5G communication system to support multiple wireless communication applications. Each of these applications requires special handling in all layers and more so in scheduler and physical layer. The present disclosure presents embodiments of dynamical creating a computation instance with a slice of resources allocated for each scheduling input. Each computation instance may be independently managed, controlled, and customized according to the specific requirements of the corresponding scheduling input. Such a dynamic resource allocation allows large number of slices in PHY layer. Furthermore, when overloading happens, one scheduling inputs may be migrated from one distribution unit (DU) to another DU without interruption for end users during scheduling migration. Accordingly, efficiency and robustness of a 5G communication system may be improved to serve multiple wireless communication applications.

Systems and methods for application aware slicing in 5G layer 2 and layer 1 using fine grain scheduling

Advances in wireless technologies have resulted in the ability of a wireless communication system to support wireless communications of different standards, e.g., 5G, LTE, and Wi-Fi. Different Wireless standards have aspects which are very different from each other. Described in the present disclosure are embodiments of architecture with hardware and software split to allow implementation of different wireless standards along a configurable signal process path. The configurable signal process path comprises software configurable operators that may be configured in a desired level of granularity to load desirable software to process signals of various standards on the same hardware. Embodiments of the disclosed architecture with hybrid hardware and software implementation may improve system operation efficiency and lower system complexity to serve communications across multiple wireless standards.

Systems and methods for hybrid hardware and software implementation of multiple wireless standards

A system and method are provided for evenly distributing central processing unit (CPU) packet processing workloads. The method accepts packets for processing at a port hardware module port interface. The port hardware module supplies the packets to a direct memory access (DMA) engine for storage in system memory. The port hardware module also supplies descriptors to a mailbox. Each descriptor identifies a corresponding packet. The mailbox has a plurality of slots, and loads the descriptors into empty slots. There is a plurality of CPUs, and each CPU fetches descriptors from assigned slots in the mailbox. Then, each CPU processes packets in the system memory in the order in which the associated descriptors are fetched. A load balancing module estimates each CPU workload and reassigns mailbox slots to CPUs in response to unequal CPU workloads.

Packet processing with dynamic load balancing

A hardware-based method is provided for allocating shared resources in a system-on-chip (SoC). The SoC includes a plurality of processors and at least one shared resource, such as an input/output (IO) port or a memory. A queue manager (QM) includes a plurality of input first-in first-out memories (FIFOs) and a plurality of output FIFOs. A first application writes a first request to access the shared resource. A first application programming interface (API) loads the first request at a write pointer of a first input FIFO associated with the first processor. A resource allocator reads the first request from a read pointer of the first input FIFO, generates a first reply, and loads the first reply at a write pointer of a first output FIFO associated with the first processor. The first API supplies the first reply, from a read pointer of the first output FIFO, to the first application.

Method and system for queuing a request by a processor to access a shared resource and granting access in accordance with an embedded lock ID

An operating system (OS) is provided including a hardware-based task scheduler, with a method for managing OS sourced tasks to be performed by a central processing unit (CPU). An OS, partially enabled as software instructions stored in a computer-readable medium and executed by the CPU, generates CPU tasks. The CPU tasks are buffered in a computer-readable task database memory. CPU task IDs associated with the buffered CPU tasks are enqueued in a CPU queue. Subsequently, the CPU dequeues a first task ID from the CPU queue, and accessing a first CPU task from the task database associated with the first CPU task ID. The CPU delivers the first CPU task to the OS. The OS generates the CPU instructions needed to perform the first CPU task, and sends the CPU instructions to the CPU for performance.

Operating system with hardware-enabled task manager for offloading CPU task scheduling

A system-on-chip (SoC) is provided with a low power processor to manage power-save mode operations. The SoC has a high-speed group with a high-speed processor, a standby agent, and a governor. In response to inactivity, the governor establishes a power-save mode and deactivates the high-speed group, but not the standby agent. The standby agent monitors SoC input/output (IO) interfaces, and determines the speed requirements associated with a received communication. In response to determining that the communication does not prompt a high-speed SoC operation, the standby agent responds to the communication. Likewise, the standby agent monitors SoC internal events such as housekeeping and timer activity, and the standby performs the tasks if it is determined that the tasks do not require a high-speed SoC operation. Alternatively, if monitored communication or internal event prompts a high-speed SoC operation, the governor activates a member of the high-speed group.

System-on-chip with power-save mode processor

A data structure splitting method is provided for processing data using a minimum number of memory accesses. An SoC is provided with a with a central processing unit (CPU), a system memory, an on-chip memory (OCM), and a network interface including an embedded direct memory access (DMA). The network interface accepts a data structure with a header and a payload. The DMA writes the payload in the system memory, and the header in the OCM. The network interface DMA notifies the CPU of the header address in the OCM. The CPU reads the header in the OCM, performs processing instructions, and writes the processed header in the OCM. The CPU sends the address of the processed header in OCM to the network interface DMA. The network interface DMA reads the processed header from the OCM and sends a data structure with the processed header and the payload.

System and method for packet splitting

The present invention provides a system, apparatus and method for providing point-to-point inter-chassis connections within chassis systems and/or network nodes. Multi-chassis systems within a network employ a protocol wherein a peer discovery process is initiated and the discovered neighbors are authentically verified before establishing an active state between point-to-point inter-chassis links.

Multi-chassis interconnect

A system and method are provided for the local distribution of stored photo-images to wireless picture frames. The method interfaces a photo-image discovery device, having no dedicated display, to a display monitor presenting a menu of photo-image user prompt options originating from the photo discovery device. A photo-image from the storage site is selected, as well as a wireless picture frame destination. Then, the photo-image is wirelessly sent to the selected destination. In one aspect, the wireless picture frame is selected in response to discovery device movements.

System and method for photo-image local distribution

A system and method are provided for peer-to-peer distributed file storage in a network of connected clients. The method transmits data file peer-storage information from a first peer node to a network-connected backup manager. The backup manager creates a mapping plan, for mapping data file segments to a peer group, which typically includes a plurality of network-connected peer nodes. The backup manager transmits the mapping plan to the first peer node. The first peer node distributes the data file segments to the peer group in accordance with the mapping plan, for storage in tangible memory media. Typically, the first peer node accepts a data file and encrypts the data file. In one aspect, the backup manager creates a mapping plan for distributing (n+x) erasure-coded segments. After receipt of the mapping plan, the first peer node creates the (n+x) erasure coded file segments in preparation for distribution.

Growing community of inventors

Cupertino, CA, United States of America

Vinay Ravuri