Lam Research Corporation

Novellus Systems Incorporated

Vinay Pohray

Sean S Kang

S M Reza Sadjadi

Rajinder Dhindsa

Andrew D Bailey, Iii

Eric A Hudson

David Wei

Ben-Li Sheu

Peter Cirigliano

David R Pirkle

Bi Ming Yen

Binet A Worsham

SiYi Li

Steve Lassig

Thomas W Mountsier

Chiu Chi

Si Yi Li

Stephan Lassig

An apparatus for etching features in an etch layer is provided. A plasma processing chamber is provided, comprising a chamber wall, a chuck, a pressure regulator, an electrode or coil, a gas inlet, and a gas outlet. A gas source comprises a fluorine free deposition gas source and an etch gas source. A controller comprises at least one processor and computer readable media, comprising computer readable code for providing a conditioning for a patterned pseudo-hardmask, wherein the conditioning comprises computer readable code providing a fluorine free deposition gas comprising a hydrocarbon gas, computer readable code for forming a plasma, computer readable code for providing a bias less than 500 volts, and computer readable code for forming a deposition on top of the patterned pseudo-hardmask, computer readable code for etching the etch layer, and computer readable code for cyclically repeating the conditioning and etching at least twice.

Wiggling control for pseudo-hardmask

A method for etching features in an etch layer. A conditioning for a patterned pseudo-hardmask of amorphous carbon or polysilicon disposed over the etch layer is provided, where the conditioning comprises providing a fluorine free deposition gas comprising a hydrocarbon gas, forming a plasma from the fluorine free deposition gas, providing a bias less than 500 volts, and forming a deposition on top of the patterned pseudo-hardmask. The etch layer is etched through the patterned pseudo-hardmask.

A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.

Lag control

The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

Trench etch process for low-k dielectrics

A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.

Method for patterning multilevel interconnects

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Fremont, CA, United States of America

Vinay Pohray