Netlogic Microsystems, Inc

Broadcom Corporation

Vinay Iyengar

Bindiganavale S Nataraj

Chetan Deshpande

Venkat Rajendher Reddy Gaddam

Sandeep Khanna

Aparna Bharat

John Zimmer

Rajagopal Krishnaswamy

A pre-computation based TCAM configured to reduce the number of match lines being pre-charged during a search operation to save power is disclosed. The pre-computation based TCAM stores additional information in a secondary TCAM that can be used to determine which match lines in a primary TCAM storing data words to be searched need not be pre-charged because they are associated with data words guaranteed to not match. The additional information stored in secondary TCAM can include a pre-computation word that represents a range inclusive of a lower and upper bound of a number of ones or zeroes possible in a corresponding data word stored in the primary TCAM.

Pre-computation based ternary content addressable memory

A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.

Cascaded content addressable memory array having multiple row segment activation

A CAM device is disclosed that includes an array of CAM cells in which the compare circuits of groups of CAM cells are connected together using a conductive layer interposed between a polysilicon layer of the CAM device and the metal-layer of the CAM device. This allows the data lines (e.g., the bit lines and/or comparand lines) of the CAM array to be formed in the metal-layer of the CAM device, which in turn allows the match lines of the CAM array to be formed in the metal-layer of the CAM device. The conductive layer, which may be a silicide layer, is connected to the match line by a via extending from the conductive layer through the metal-layer to the metal-layer.

Content addressable memory array having local interconnects

An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.

Integrated circuit with reconfigurable inputs/outputs

A method may include, in response to a single command and an N-bit segment value, generating a search key comprising M segments for at least one of a plurality of different databases, the N-bit segment value forming different ones of the M search key segments according to a database configuration of the at least one database.

Processor with compare operations based on any of multiple compare data segments

Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matching condition of another cell block. By selectively enabling cell blocks during search operations only when needed, energy consumption is reduced. Selectively enabling a cell block includes selectively pre-charging match lines to the cell block, selectively enabling word lines to the cell block, and selectively enabling comparand line to the cell block. In accordance with certain embodiments, the CAM device is configurable to perform search operations in a pipelined manner. Accordingly, the CAM device is capable of performing multiple search operations simultaneously.

Segmented content addressable memory device having pipelined compare operations

A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and generates a feedback signal based on the detected match line voltage. The pre-charge circuit adaptively charges the match line in response to the feedback signal.

Adaptive match line charging

A content addressable memory (CAM) device includes a CAM array and a configuration circuit. The CAM array has a plurality of rows of CAM cells, each row segmented into a plurality of row segments, each row segment including a plurality of CAM cells coupled to a corresponding match line segment, and a match line control circuit having an input coupled to the corresponding match line segment, an output coupled to the match line segment in a next row segment, and a control terminal to receive a corresponding enable signal. The configuration circuit has an input to receive configuration information indicative of a width and depth configuration of the CAM array and having outputs to generate the enable signals.

Low power content addressable memory device having selectable cascaded array segments

A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array includes a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein the control circuit has an input to receive a corresponding sub-array enable signal. The partition logic has an input to receive a partition select signal, and is configured to generate the sub-array enable signals in response to the partition select signal. The control circuits selectively propagate the search key through the sub-arrays in response to the sub-array enable signals.

Dynamically partitioned CAM array

A processor device integrated circuit can include a plurality of storage locations logically configurable into at least one database. Such a database can include a number of records, record having a selectable size of up to F multi-bit segments, where F is an integer greater than one. A search key application circuit can apply a search key value of up to F multi-bit segments to the at least one database in response to receiving one search key segment value. The one search key segment can be applied as any of the F multi-bit segments according to a segment selection value.

An integrated circuit device can include a plurality of configuration storage locations each comprising at least one encoding field. Each encoding field can selectively enable at least one received data value to be encoded into an encoded data value prior to being applied to a corresponding block of the integrated circuit device. Each block can comprise a plurality of content addressable memory (CAM) cells.

Selective encoding of data values for memory cell blocks

A method of testing a semiconductor device having a pipelined architecture. Operation of a first pipeline stage of the semiconductor is disabled during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device. A second pipelined operation is executed to enable the second pipeline stage to generate an intermediate result using the test data. A final result of the second pipelined operation is evaluated to determine whether the second pipeline stage produced a correct intermediate result.

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Cupertino, CA, United States of America

Vinay Iyengar